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February 22, 2016
Floorplanning complex SoCs with multiple levels of physical hierarchy
How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
Article | Topics:
IP - Assembly & Integration
,
EDA - IC Implementation
| Tags:
floor planning
,
hierarchical design
,
multiply-instantiated blocks
,
pin placement
,
power routing
| Organizations:
Synopsys
EDA Topics
DFM
DFT
ESL
IC Implementation
Verification
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