Verilog-AMS

December 14, 2010

Characterizing PLL jitter from power supply fluctuations using mixed-signal simulations

Characterizing PLL jitter is important yet challenging. Usually done through transistor-level transient analysis, a slow simulation speed has been the major bottleneck preventing jitter from being characterized in a timely manner. This paper presents an approach for fast jitter characterization using mixed-signal simulation (a combination of transistor-level blocks and calibrated behavioral models). Among various PLL [...]
Article  |  Topics: EDA - IC Implementation  |  Tags: ,

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