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Boolean equivalence checking
Boolean equivalence checking
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May 30, 2016
Comparing your design to itself – a crucial part of verification
Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.
Expert Insight | Topics:
EDA - Verification
| Tags:
Boolean equivalence checking
,
clock gating
,
formal verification
,
sequential equivalence checking
,
X propagation
| Organizations:
Synopsys
EDA Topics
DFM
DFT
ESL
IC Implementation
Verification
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