We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
The strategy of designing for best power rather than for best timing in place-and-route delivers better results all around.
How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.
How EDA tools are evolving to make it possible to design with finFET processes.
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
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