semiconductor

Microelectromechanical systems (MEMS) manufacturing continues to be dogged by a technologically and economically inefficient landscape where too many products demand their own bespoke processes and packages. However, the last three years have seen third-party foundries gain more influence over the sector, bringing greater demands for reuse and DFM considerations, earlier in the design flow. The [...]

This year's Design Automation and Test in Europe conference heard from a broad range of users and suppliers about the challenges to and solutions for getting optimal yields at advanced process nodes, particularly as the industry advances toward 22nm. This article recaps presentations by four executives at the Dresden-hosted event: Pierre Garnier of Texas Instruments, [...]

Designers have been using dummy fill to address design for manufacturing for some time, but the process of simply wallpapering shapes into a design's "white space" to help it maintain planarity can no longer cope with the complex challenges presented at today's advanced process nodes. Not only is planarity harder to maintain, but there are [...]

Engineering managers need to get their priorities in order for incoming process nodes, says analyst Gary Smith

The purpose of this special issue of EDA Tech Forum is to try and cut through some of the confusion and even frustration that surrounds DFM as a concept. We cannot promise “DFM for Dummies,” but we do hope to give you a sense of how you might manage the process.

Technological advances are often driven by the need to simplify and control a task. Silicon test is a good example. Its requirements are continuously increasing in complexity and this process drives the development and adoption of automated test strategies. A thorough approach to manufacturing test is essential to the delivery of high-quality devices. A whole-chip […]

During the CEO Panel at this year’s Design Automation Conference, the men leading the three largest EDA vendors stressed that their industry can do well in a slump because it both contributes to the ongoing battle against technological limits, and enables the delivery of ever greater efficiency. But another, parallel question raised by this year’s […]

The article provides an overview of one common theme in the papers presented at a special session of the 2009 Design Automation Conference, Dawn of the 22nm Design Era. As such, we would recommend that readers wishing to access still more detail on this topic (in particular, on device structures for 22nm and project management […]

The article presents the context for the use of computation scaling (CS) to eke out more from existing lithography tools until next-generation techniques are finally introduced. It discusses the critical elements in the CS ecosystem developed by IBM and partners to overcome roadblocks to optical scaling that demand the use of non-traditional techniques for the […]

Chemical mechanical polishing (CMP) has traditionally been considered an enabling technology. It was first used in the early 1990s for BEOL metallization to replanarize the wafer substrate thus enabling advanced lithography, which was becoming ever more sensitive to wafer surface topography. Subsequent uses of CMP included density scaling via shallow trench isolation and interconnect formation […]