December 4, 2012
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
November 5, 2012
20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
October 11, 2012
Manufacturability, routing, library design and more - it all needs rethinking at 20nm, writes Tong Gao of Synopsys.
October 9, 2012
Finding and fixing double patterning problems in 20nm designs
September 12, 2012
A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
September 6, 2012
Antun Domic of Synopsys tackles the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
June 1, 2012
There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
