EDA

Open-source toolchains give companies ultimate control over their development environments, but how many can really afford the resources to debug and develop their own tools? Would they be better off with a commercially supported open-source approach?

The article describes a novel optimization approach that extends leading methodologies to improve performance, power and area. It is based on a pre-generated cell library that extends commercially available foundry libraries and couples it with novel logic optimization to aim for the delivery of near full-custom performance levels. The approach assesses the gate-level netlist generated [...]

We report from National Instruments’ annual user conference, NIWeek 2011, held in a sizzling Austin last month.

Mentor’s Dennis Brophy, Cadence’s Stan Krolikoski and Synopsys’ Yatin Trivedi describe how you can prepare to adopt Accellera’s Universal Verification Methodology.

The description of the stimulus to a device-under-test is becoming ever more complex. Complex constraint relationships need to be defined, and the use of randomly generated stimulus to achieve comprehensive coverage metrics is proving less predictable and more labor-intensive. Using the combination of a graph-based stimulus description with a more intelligent algebraic constraint solver, a [...]

We talked to Mentor Graphics CEO Wally Rhines about the solutions that already exist to combat increasing design complexity.

The article offers a case study of the DFM planning and methodology applied during a shrink of Cambridge Silicon Radio's UF6000 system-on-chip from the 130nm to 65nm.

Lane Mason Marc Greenberg DDR3 DRAMs still languish around the edges of the market despite their supposed attraction in terms of power and performance, the widespread availability of product, and the presence of a supposedly ‘evolved’ ecosystem and implementation infrastructure. Just over 18 months ago, Intel launched a major Go To DDR3 market initiative at […]

New tools and standards encourage communication between the electrical and mechanical domains, says Pawel Chadzynski. Most major electronics companies have separate electrical (ECAD) and mechanical (MCAD) design organizations. Efficient collaboration between these teams throughout the PCB design process can significantly reduce cycle times, lower the risk of re-spins, and improve quality. The first challenge to […]

Floorplanning informed by thermal analysis can significantly improve PCB layouts, writes Robin Bornoff The number of PCB design constraints seems ever increasing. The risk that a design will fail either functional performance or reliability goals grows for each generation. One increasingly popular trade-off addresses a balance between thermal compliance and signal integrity. Components with high […]