TSMC Altera heterogeneous integration is cool but is it 3D?
This looks more like 2.5D silicon interposer-based technology to us, though it is a major and necessary advance
This looks more like 2.5D silicon interposer-based technology to us, though it is a major and necessary advance
The headlines from DATE, CPTF and CDN Live. The latest technical articles. And new features. Our regular update.
Colin Walls of Mentor Graphics on a significant surprise in UBM’s latest market survey
We look at the upcoming Synopsys and Mentor Graphics user meetings in Santa Clara.
It’s time for everyone to start thinking about how to handle the incoming finFET age.
Beyond the earthquake, analyst IHS says the tragedy revealed systemic problems with an aging semiconductor fab base
Future Horizons’ Malcolm Penn warns of capacity crunch later this year
This page brings together all of our coverage from Design Automation and Test in Europe 2012 in Dresden, Germany.
Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL
Until the software is ready, it’s often hard to tell when two neighbouring units on an SoC could combine to push the package past its maximum thermal point. Docea Power aims to help.