low-power design

April 28, 2014

Overcoming the power/performance paradox in processor IP

The configurability of processor IP such as Synopsys' ARC HS family gives designers the option to optimise for power, performance or a combination of both.
Article  |  Topics: IP - Selection  |  Tags: , ,   |  Organizations:
April 16, 2014
Pranav Ashar

Reset optimization pays big dividends before simulation

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
January 30, 2014
Colin Walls

Power management in embedded systems – new thinking required

Effective low-power design for embedded-systems will take a new culture of close collaboration between hardware and software engineers.
November 1, 2013
Jack Erickson is director of product management at Cadence Design Systems.

Slow winter or new spring for hardware design?

Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
Expert Insight  |  Topics: EDA - ESL  |  Tags: , , ,   |  Organizations:
September 24, 2013
Hybrid memory cube architecture

DRAM interfaces for mobile and networking designs

Mobile and networking platforms need high bandwidth, low power consumption, and small footprint. These needs drove standards, such as LPDDR4, Wide I/O 2 and Hybrid Memory Cube.
Article  |  Topics: IP - Selection  |  Tags: , , , , , , ,   |  Organizations:
March 1, 2009

The power-aware OS

The article describes the context and need for embedded operating systems that are more responsive to the power management demands placed on today’s electronic devices. It reviews the design objectives for the two main types of power management, reactive and proactive, and examines how both can be implemented. For system developers designing portable electronic devices, […]

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