low-power design

May 3, 2021
Static checks May 2021

How automated static checks help verify complex circuits for better performance and reliability

Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
October 16, 2019
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Achieving the interactive development of low-power designs

Power intent files have increased efficiency and the use of an IDE can prevent them becoming outdated as a design evolves.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , , , , , , ,   |  Organizations:
August 5, 2015
Power switch

‘Even the software guys are starting to talk in milliwatts’

System-level power is the next frontier for a power-intent standard – or rather a collection of them – being developed by a partnership between Accellera, Si2 and the IEEE.
May 25, 2015
Evaluation board used by TI for testing the CTPL library

Handling power dropouts in MSP430 energy-harvesting designs

Software for energy-harvesting designs needs to cope with sudden power failures. FRAM storage can reduce the power and performance penalties of full resets.
May 15, 2015
Four-core Cortex-A72 layout example

Cortex-A72: microarchitecture tweaks focus on efficiency

ARM has revealed a number of details of the microarchitecture that underpins its flagship Cortex-A72 as the processor moves towards its production release.
January 20, 2015
Veloce2 emulator

Assertion-based emulation

Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
January 7, 2015

A holistic approach to IoT chip design

A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
November 23, 2014
Cadence Palladium cluster

Acceleration homes in on power issues

Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.
October 18, 2014
Soft-blocked floorplan

Placement optimizations push power and clock on Cortex-M7 project

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
October 6, 2014
Power grid signal track blocking

ARM, TSMC design explores 16nm finFET issues

ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,   |  Organizations: ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors