The strategy of designing for best power rather than for best timing in place-and-route delivers better results all around.
Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
Power intent files have increased efficiency and the use of an IDE can prevent them becoming outdated as a design evolves.
System-level power is the next frontier for a power-intent standard – or rather a collection of them – being developed by a partnership between Accellera, Si2 and the IEEE.
Software for energy-harvesting designs needs to cope with sudden power failures. FRAM storage can reduce the power and performance penalties of full resets.
ARM has revealed a number of details of the microarchitecture that underpins its flagship Cortex-A72 as the processor moves towards its production release.
Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.
Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
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