Synopsys

November 6, 2017
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Using sequential equivalence to verify clock-gating strategies

Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques such as clock gating or register re-timing.
Article  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
November 6, 2017
Rich Collins of Synopsys

Fighting the war of escalation in embedded systems security

The challenge for designers is to find ways of providing high levels of security in low-cost devices that have become worthwhile targets because of their role as gateways to more valuable information.
Expert Insight  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , ,   |  Organizations:
September 26, 2017
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Combining USB Type-C and DisplayPort support in portable implementations

Using USB Type-C connectors to combine both USB-C 3.1 and DisplayPort data streams, to support data, audio, video and power connections on a single port
Article  |  Topics: IP - Selection  |  Tags: , , , ,   |  Organizations: ,
August 7, 2017
Pedro Ricardo Miguel

Supporting higher-resolution displays without major system redesign

Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.
Expert Insight  |  Topics: Embedded - Architecture & Design, IP - Assembly & Integration  |  Tags: , , , , ,   |  Organizations: , ,
July 18, 2017
Richard Solomon, technical marketing manager, Synopsys

Using CCIX to implement cache coherent heterogeneous multiprocessor systems

CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.
Expert Insight  |  Topics: Embedded - Architecture & Design, IP - Assembly & Integration, Selection  |  Tags: , , ,   |  Organizations: ,
July 11, 2017
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Applying sub-threshold circuit techniques to IoT device design

Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity.
Article  |  Topics: Embedded - Architecture & Design  |  Tags: , ,   |  Organizations:
June 29, 2017
Gordon Cooper

High-resolution visual recognition needs high-performance CNNs

Quadrupling the performance of a dedicated CNN engine within an embedded vision processing core brings more complex graph processing within reach.
Expert Insight  |  Topics: Embedded - Architecture & Design, IP - Selection  |  Tags: , , , , ,   |  Organizations:
June 16, 2017
Dana Neustadter is a senior manager of product marketing for Synopsys’ Security IP solutions.

Protecting content transmitted over USB Type-C connections

SoC developers who want to use USB Type-C in their designs will have to implement HDCP 2.2 content protection so that the target devices will be able to play protected content.
Expert Insight  |  Topics: IP - Selection  |  Tags: , ,   |  Organizations:
June 7, 2017
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Staging virtual prototype bring-up for faster software development

How staging virtual prototype bring-up can accelerate the development of embedded software in complex systems.
Article  |  Topics: Embedded - Integration & Debug, EDA - Verification  |  Tags: , , ,   |  Organizations:
May 24, 2017
Michael Thompson is the senior manager of product marketing for the DesignWare ARC processors at Synopsys

Building processors to enable intuitive human-machine interaction

The increasing complexity of human-machine interfaces is challenging processor designers to produce the necessary performance within a limited power budget
Expert Insight  |  Topics: IP - Selection  |  Tags: , , ,   |  Organizations:

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