Antifuse-based OTP NVM is highly scalable, has the area efficiency to enable macros of megabit capacities, and offers low read power.
The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
The basics of USB 3.2, how to implement it in an SoC, and how USB Type-C connectors and cables are used in USB 3.2 systems.
As AI becomes pervasive in computing applications, so too does the need for high-grade security in all levels of the system.
The proliferation of attacks against embedded systems is making designers realize that they need to do more to secure their products and ecosystems.
Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
Machine-learning strategies for embedded vision are evolving so quickly that designers need access to flexible, heterogenous processor architectures that can adapt as the algorithms evolve.
Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.
Designers need to understand how the architecture of electronic control units used to implement ADAS in vehicles is changing.
Choosing the right crypto processor implementation involves a complex set of design tradeoffs between speed, area, power consumption and flexibility. Using consistent benchmarks can help explore your options.
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