Understanding DDR SDRAM memory choices
This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.
Synopsys
Using advanced IP to build SoCs for hyperscale data centres
SoC suppliers building the key components for hyperscale data centres need access to the latest IP to handle functions such as PCIe, DDR5, cache coherency, NVMe SSDs, and the highest-bandwidth Ethernet implementations.
Enabling the move to a system-centric view
Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
Low-power debugging made easy
UPF provides a useful way to describe the power-management strategies that should be applied to a design, but using it introduces a number of challenges during low-power debugging.
Optimizing the hardware implementation of machine learning algorithms
Optimizing the way in which machine learning algorithms are implemented in hardware will be a major differentiator for SoCs, especially for edge devices.
The antifuse advantage for one-time programmable non-volatile memory
Antifuse-based OTP NVM is highly scalable, has the area efficiency to enable macros of megabit capacities, and offers low read power.
Verifying clock domain crossings in UPF-based low-power SoCs
The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
Understanding USB 3.2 and Type-C
The basics of USB 3.2, how to implement it in an SoC, and how USB Type-C connectors and cables are used in USB 3.2 systems.
Why AI needs security
As AI becomes pervasive in computing applications, so too does the need for high-grade security in all levels of the system.
Using threat models and risk assessments to define device security requirements
The proliferation of attacks against embedded systems is making designers realize that they need to do more to secure their products and ecosystems.