Implementing high performance, low power Bluetooth Low Energy interfaces in SoCs
A look at the complexiites of implementing a Bluetooth Low Eenergy interface in an SoC.
The Bluetooth Low Energy (BLE) specification was introduced in 2011. It has been adopted rapidly, and is being used by developers of system-on-chips (SoCs) for the Internet of Things (IoT) to extract long operating and standby times from batteries. This helps cut the costs of creating wireless sensor networks and other IoT ecosystems, accelerating their adoption.
According to the 2019 Bluetooth Market Update, more than one third of all Bluetooth devices will have low-energy features by 2023. To drive such rapid growth, SoC designers need to be able to integrate a BLE radio into their SoCs with ease.
A few SoC vendors have developed their own BLE radios, but this is becoming more difficult as the standard evolves and their designs target advanced process nodes. Challenges include keeping costs down, staying in line with standards, and ensuring flexibility. Third-party IP vendors, on the other hand, can spread their R&D costs across many implementations, as well building deep expertise in both the standard and how it is used.
Deciding how to implement Bluetooth LE is complex, because it is hard to make accurate trade-offs between power consumption and circuit performance in the dynamic context of a Bluetooth connection. In this article we explore some of the key challenges of implementing BLE in an SoC, using the Synopsys Designware Bluetooth IP as a model. It was developed to offer low power and high performance, as these specs show:
- Receiver sensitivity
-96dBm @ 1.0Mbit/s
-93dBm @ 2.0Mblt/s
-100.5dBm IEEE 802.15.4
- Receiver intermodulation performance
-35dBm dual-tone interferer @ -64dBm received signal
- -20dBm to +6dBm transmit output power
- Current consumption at 1.1V (including soft IP modem)
5.7mA @ receive mode
6.9mA @ 0dBm transmit mode
Sensitivity, the key performance indicator, is -96 dBm, achieved for a current draw of 5.65mA at 1.1V.
This combination of performance and power consumption must be maintained without reducing connection quality and robustness, especially during interference. The main specifications for robustness and connection quality are selectivity, blocking, and intermodulation performance. The first two can be achieved through filtering, but intermodulation performance demands a careful trade-off between sensitivity and power consumption to meet the specification’s requirements. The Synopsys Bluetooth IP achieves an intermodulation performance of -35dBm, 15dB better than the standard requires.
A BLE implementation must also work well in all applications, and so needs both the radio physical interface (the PHY) and the link layer controller (LLC) to be flexible and optimised.
The Bluetooth PHY
Figure 1 shows the block diagram of the PHY. The receiver (RX) is a low-IF topology. The transmitter (TX) directly modulates the frequency synthesizer. The modem supports both BLE 5.1 and IEEE 802.15.4.
The RF front end works with an integrated antenna-matching network, enabling effective co-optimisation and the implementation of a single-pin direct RF connection to the antenna. The design also makes it possible to choose the impedance of the low-noise amplifier (LNA) at the input to the receiver and the power amplifier (PA) at its output independently. This enables both to be optimised without concerns about mutual loading.
To guarantee drift-free high performance despite temperature or battery-voltage variations, all the critical circuits in the PHY are re-calibrated in the background. This ensures that the IP keeps the same performance throughout the battery’s lifetime.
The PHY uses extensive digital assistance, such as digital monitoring of functional blocks and the application of digital signal processing. This reduces the impact of analogue variability and non-linearities. The PHY can also be woken quickly, to maximise the IP’s sleep time. The crystal oscillator has an accelerator block so it can wake and provide a stable clock in 160ms.
A lot of attention has been paid to isolation, to make it easy to integrate the block in an SoC. All the major analogue and RF blocks in the PHY have separate supplies, each isolated by an low-dropout (LDO) regulator designed to achieve a high power-supply rejection ratio. Sensitive analogue blocks are protected inside deep n-well islands, and guard rings are used to isolate the local substrate.
Figure =1 Block diagram of the Bluetooth Low Energy 5.1 PHY (Source: Synopsys)
The Bluetooth controller
The PHY is controlled by the LLC, with functions implemented in hardware and in a host CPU, which also runs the software stack and application. The CPU must be in sleep mode during TX and RX operations to maintain RF performance and minimise peak current draw, so all the time-critical LLC functions for running the PHY are implemented in hardware. Functions that can run before or after TX/RX events are run in firmware, as per Figure 2.
The LLC hardware includes co-processors to handle lengthy operations that would otherwise take multiple CPU cycles. These include a channel selection co-processor, and a 128bit Advanced Encryption Standard engine to handle security operations.
The LLC also has a clock and power management unit that selectively disables unused digital blocks and gates their clocks to avoid wasting power. The same unit also controls the PHY’s wake/sleep modes, including bring-up sequences, timings and calibration, and makes details of this activity available to the SoC’s power management unit.
Figure 2 The operating modes of a typical BLE event (Source: Synopsys)
Estimating power consumption
The challenge in estimating the power consumption of a Bluetooth LE PHY implementation is to develop meaningful and repeatable use cases. Here are three sets of actual measurements for real scenarios implemented using the Synopsys Bluetooth IP in a 40nm process. Results for the controller and software stack are simulated using typical figures for IP processor blocks.
The first scenario is an advertising event, in which the advertiser transmits ADV_IND events and waits for SCAN_REQ on the three advertising channels. The payload size is 6 bytes and the advertising interval is 100ms. Figure 3a shows the current profile during pre-event processing, transmission, three reception phases, and post-event processing. The average current consumption is 61mA from a 1.1V supply. Using an 85% efficient DC-DC converter, this will mean a 26.3mA current draw from a 3V Li-Ion battery, which in turn translates into a 1.6 month operating lifetime from a 30mAh coin cell.
Figure 3a Graph showing pre-event processing, transmission, three reception phases, and post-event processing (Source: Synopsys)
The second scenario involves a sensor operating as a peripheral device with a single connection. The device sends an empty PDU packet every second unless there is information that needs to be sent, making this an extremely low power application. See Figure 3b.
Figure 3b Arbitrary sensor operating as a peripheral device (Source: Synopsys)
The average current consumption of 8.6mA includes 1.2mA for periodic recalibration to compensate for temperature and battery-voltage variations. If the PHY is powered directly from a 1.5V coin cell the sensor’s operating lifetime will be about 4.8 months.
The third scenario is a peripheral that exchanges data with a central device at high throughput. The device exchanges 251 bytes in both directions every 7.5ms. This is a demanding application with relatively high power consumption. See Figure 3c.
Figure 3c Peripheral exchanging data with a central device at high throughput (Source: Synopsys)
The average current consumption is 3.54mA. Using the same DC-DC converter as in the first scenario results in a current draw of 1.5mA from a 3V Li-Ion battery. Using a 30mAh coin battery, the operating lifetime would be 20 hours.
Conclusion
BLE technology is enabling the development of low-power IoT devices that can enable the creation and deployment of large IoT ecosystems, as well as attractive standalone devices.
However, it is not trivial to design, verify, validate and integrate a standards-compliant Bluetooth LE 5.1 interface in an SoC, especially one being implemented on an advanced process.
To implement Bluetooth LE, designers either need to develop extensive insights into how the standard works, what the design trade-offs are, and how to measure key characteristics such as signal robustness and power consumption in a wide range of operating scenarios, or find another way forward.
Synopsys has already done this work and more in its Bluetooth 5.1 compatible Bluetooth LE IP block. Extensive co-optimisation of features such as the RF front-end and the antenna matching-network, and partitioning of TX/RX operations between hardware and firmware, have enabled the development of a robust and power-efficient IP block that can bring this important interface to SoCs being implemented into processes at 40nm and soon, more advanced process nodes.
Authors
Carlos Azeredo Leme, senior staff engineer, Synopsys
Ahmed Ibrahim, senior manager, digital design and verification, Synopsys/Silicon Vision
