Getting ready for 20nm
Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
Industry Blogs
Verification challenges require surgical precision
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Making dummy fill smarter
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
No more spaghetti
Cutting the cabling to simplify the emulation process.
The return of the ‘custom’ embedded OS
Colin Walls of Mentor Graphics on a significant surprise in UBM’s latest market survey
New SystemC reference simulator open for public comment
A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy.
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