September 6, 2012
Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
August 23, 2012
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
May 22, 2012
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
April 25, 2012
Cutting the cabling to simplify the emulation process.
March 21, 2012
Colin Walls of Mentor Graphics on a significant surprise in UBM’s latest market survey
February 9, 2012
A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy.