Facing the verification management challenge
The growing verification challenge, and how to address it by coordinating multiple debug strategies.
Design Management
Debugging the debug challenge
Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
Optimizing cloud computing for faster semiconductor design
How Cadence, Intel and Xuropa accelerated the semiconductor design process by squeezing 15% more capacity out of a virtualized server farm
Raising the bar to manage R&D and ROI
Semiconductor companies are hustling to grow revenues, stay on the razor’s edge of technology and remain one step ahead of their customers’ needs. All this is going on while the industry is undergoing wrenching change. The end of 2009 finds the chip business at a crossroads. It has been more than 60 years since the […]
Improving team productivity with efficient data management for SoC designs
The efficient management and synchronization of design data is now a necessity and no longer something that is a ‘nice-to-have’. Design complexity continues to increase with one result being that development spreads across several groups (often in different places). A project may also have several thousands design files generated by various tools from different vendors […]
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