Why cell-aware testing is important
Characterizing standard-cell defect mechanisms helps improve IC testing
EDA Topics
DAC 2012: 20(nm) questions
There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
Making dummy fill smarter
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
Effective finger-pointing: the art of modern yield analysis
Correlating production test failure diagnosis with DFM analysis can help identify and understand systematic yield issues, and to find out whether they are linked to DFM violations.
Where there’s a will… there’s a way to better VHDL verification
An overview of the Open Source VHDL Verification Methodology and two of the libraries it uses.
Modelling envelope-tracking RF PAs for LTE at high dynamic range
Current techniques for modelling RF power amplifiers don't provide the dynamic range necessary to simulate their performance properly when used in the energy-saving envelope-tracking mode necessary to give LTE terminals a decent battery life.
Decoupled constraint modelling – a design methodology for hard real-time systems on chip
Using UML to define a software-defined modem SoC in terms of decoupled constraints - the order of activities, the timing they have to meet, and the available resources
Emulation delivers energy efficiencies and economies of scale
Can emulation save energy and space, as well as time, during the verification process? Some argue so.
No more spaghetti
Richard Pugh reflects on efforts to cut through the tangle of cables and make emulation easier.
What can FPGA-based prototyping do for you?
This extract from the Synopsys and Xilinx-authored "FPGA-Based Prototyping Methodology Manual" outlines a number of valuable strategies supported by brief project case studies.
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