Platforms

Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.

This second part looks at Mentor's views on flow neutrality, how DRS360 was born, machine learning and the threat from embedded Trojans.

Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.

Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.

By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.

System-level power is the next frontier for a power-intent standard – or rather a collection of them – being developed by a partnership between Accellera, Si2 and the IEEE.

How agile methodologies can be applied to personal and team practice in IC design, including for developing cloud accelerators at Microsoft

Is it worth trying to iron out all the bugs in an SoC before taping out, or should design teams anticipating a re-spin go to silicon earlier and use the chips that come back as verification accelerators?

How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.

How Xilinx' Vivado HLS enabled the creation of an in-fabric, processor-free UDP network packet engine