Chipmaker

July 20, 2015
TSMC finFET

Lessons learned in the finFET trenches

In sessions at the 2015 Design Automation Conference, engineers who had worked on finFET-oriented projects revealed how the technology has changed their design practices and where others may want to think twice about making the move.
June 25, 2015

Applying agile techniques to IC design

How agile methodologies can be applied to personal and team practice in IC design, including for developing cloud accelerators at Microsoft
May 25, 2015
Evaluation board used by TI for testing the CTPL library

Handling power dropouts in MSP430 energy-harvesting designs

Software for energy-harvesting designs needs to cope with sudden power failures. FRAM storage can reduce the power and performance penalties of full resets.
May 15, 2015
Four-core Cortex-A72 layout example

Cortex-A72: microarchitecture tweaks focus on efficiency

ARM has revealed a number of details of the microarchitecture that underpins its flagship Cortex-A72 as the processor moves towards its production release.
May 6, 2015

Fixing late ECOs in ARM core subsystems at STMicroelectronics

Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
April 20, 2015

Developing and integrating configurable GPU IP using FPGA-based prototyping

How Imagination Technologies used FPGA-based prototyping to develop its GPU IP and integrate it into a real world system
April 3, 2015
Early and accurate power estimation - feat img

A better method for early and accurate power estimation

Early and accurate SoC power estimation is possible, says Broadcom, thanks to a technique that maps simulation results between gate and RTL representations
Article  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations: ,
March 16, 2015
Brian Fuller is editor in chief at Cadence Design Systems.

Design reaches out from the edge

We are moving towards a "continuum of compute", ARM CEO Simon Segars said at CDNLive Silicon Valley, a trend that will reshape design.
January 30, 2015

Mixed-signal verification of advanced SoCs using VCS AMS

How ST Microelectronics uses Synopsys' VCS AMS, combining VCS functional verification and CustomSim, to verify one of its mixed-signal designs
Article  |  Topics: IP Topics, EDA - Verification  |  Tags: , , , , ,   |  Organizations: ,
January 26, 2015
Silicon Photonics litho featured image

How lithography simulations enable silicon photonics

Precise curved geometries are vital to making this emerging and cost-effective CMOS-based technology work. This primer explains its advantages and how litho tools are evolving to meet the challenges it presents.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors