DAC 2016 preview: Real Intent
The functional verification specialist will discuss the latest updates to Ascent and Meridian – and offer top quality espresso at this year’s conference.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
DAC 2016 preview: Mentor Graphics
An overview of the vendor’s busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.
Register tools appear ahead of DAC
Ahead of June’s Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.
ECC crypto code and core aim for home automation
Oberon Microsystems has ported a set of low-overhead cryptographic codes suitable for Apple’s HomeKit to the Cortus APS3RP 32bit processor core.
DAC 2016 preview: Gary Smith EDA
The company’s annual ‘What to see’ list is now available for download and highlights some of EDA’s less recognized areas of innovation.
Mentor integrates automotive IGBT test and simulation
A new dedicated automotive power tester helps cut simulation errors to just 0.5% with more faithful calibration.
Cloud analysis comes to power grid design
Ansys has decided to marry cloud computing with some of the tools used in SoC design that can make use of large amounts of temporary computer power.
ARM completes multicore test chip on 10nm finFET
ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC’s upcoming 10nm FinFET process technology.
Functional safety and high reliability for FPGA designs – eight videos show you how
Videos detail techniques to improve the functional safety and reliability of FPGA designs, including the implementation of triple modular redundancy, safe FSM schemes and self monitoring.
Allegro release tackles new generations of PCB
The latest release of Cadence’s Allegro deals with flex PCBs, material inlays as well as tighter links to signal integrity.