Synopsys adds ultra-low power security processor IP
Ultra-low power security processor IP includes defences against side-channel attacks, data and instruction encryption, DSP options for sensor processing and more.
Ultra-low power security processor IP includes defences against side-channel attacks, data and instruction encryption, DSP options for sensor processing and more.
A look at some of trade-offs involved in building large system memories for enterprise equipment using DDR4 IP.
Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.
EEMBC has released version 2.0 of its suite for measuring the performance of automotive powertrain tasks on multicore processors.
Accellera has moved to an Apache 2.0 open-source license for all of the supplementary materials for its SystemC library.
Wally Rhines headlines as keynote at free technical events set for Shanghai on August 30 and Beijing on September 1.
Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.
The International Electron Device Meeting has pushed back the deadline for its papers to get the latest developments in process and device design into the December conference.
SoftBank cites IoT as its main reason for buying ARM, but could it change the relationship between customers and the processor designer?