June 13, 2012
In his opening keynote at the VLSI Technology Symposium on Tuesday, Intel director of components research Mike Mayberry provided four ways to look into what is from today’s perspective a very foggy future.
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June 12, 2012
You want finFETs with different threshold voltages on the same SoC? Forget what the FD-SOI guys tell you: it’s possible. At least with a certain amount of performance loss, say IBM and GlobalFoundries.
June 12, 2012
During his CEDA talk at DAC last week Professor Mark Horowitz challenged the audience to find holes in the approach he and his team have been developing over the past few years to rethink analog design.
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June 11, 2012
FinFET or trigate structure provide a number of degrees of freedom in design in the battle against DIBL – and one of those dimensions is doping, Professor Tsu-Jae King Liu explained in a course ahead of the 2012 VLSI Symposia this week.
June 11, 2012
Cognovo is running a webinar next week (19 June) on model-driven design for software-defined wireless modems.
June 11, 2012
A deal between GlobalFoundries and STMicroelectronics has answered the question as to where ICs based on an FD-SOI process can be made, and not just for ST.
June 7, 2012
Expose your transaction-level innovations to the real world early on and catch bugs before simulation.
June 6, 2012
Accellera has approved version 1.0 of the Unified Coverage Interoperability Standard (UCIS). Here’s how it works.
June 6, 2012
Intel’s Ivy Bridge series of processors were designed from the outset to be split apart and recombined to create variants of the base platform, Intel architecture project manager Brad Heaney explained during the Wednesday keynote session at DAC 2012.
June 5, 2012
Foundries can’t hand down design rules on tablets of stone any more – success at 20nm will take close collaboration with customers and tool vendors