Many IoT applications have a very strict energy budget. SoC designers targeting the IoT have to trade off providing the features that the market demands with the power budget the applications demand. What are their options?
Using formal property verification to prove that SoCs can’t do the wrong thing, as well as that they will do the right thing.
How parallelism in project management, synthesis and processing resources can accelerate FPGA-based design
Achieving IoT security means addressing every link in the chain, from the quality of your application code to embedding a root of trust in the hardware.
How to save test time and test costs by doing more tests in parallel, increasing compression, pooling tester memory, managing branching - and more
Part three of our series looks at the choices you face as you decide whether to build or buy a board.
Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.
A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
Part two of our series on FPGA-based prototyping looks at two critical factors to address before a project begins: budgeting and high-level implementation.
This multi-part series addresses various aspects of FPGA-based prototyping. Future installments will address budgeting and implementation, but we start by looking at why the technique is generating so much interest.
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