Synopsys

January 27, 2016
Dr Lauro Rizzatti, verification consultant

Hardware emulation answers Brooks’ Law

What can you add to a challenging project without pushing out deadlines and muddling communication?
January 20, 2016

Using end-to-end prototyping to reduce the impact of rising software content in SoCs

A look at using end-to-end prototyping to ease architecture development, hardware/software integration, and system validation in SoC designs
January 19, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Reachable or reached, covered or coverable – is it just semantics?

How code coverage and reachability analysis differ between simulation and formal verification techniques, and ways to use that to advantage.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , ,   |  Organizations:
January 12, 2016
Angela Raucher is product line manager for Synopsys’ ARC EM processors.

Processor configuration for low-power IoT applications

Many IoT applications have a very strict energy budget. SoC designers targeting the IoT have to trade off providing the features that the market demands with the power budget the applications demand. What are their options?
Expert Insight  |  Topics: IP - Assembly & Integration, Selection  |  Tags: , ,   |  Organizations:
January 5, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Thought you had verified your SoC? You probably only did half…

Using formal property verification to prove that SoCs can’t do the wrong thing, as well as that they will do the right thing.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
November 30, 2015

How to accelerate FPGA design productivity at every available step

How parallelism in project management, synthesis and processing resources can accelerate FPGA-based design
Article  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
November 24, 2015
Angela Raucher is product line manager for Synopsys’ ARC EM processors.

Taking an end-to-end approach to IoT security

Achieving IoT security means addressing every link in the chain, from the quality of your application code to embedding a root of trust in the hardware.
November 6, 2015

Reducing test costs through multisite and concurrent testing

How to save test time and test costs by doing more tests in parallel, increasing compression, pooling tester memory, managing branching - and more
Article  |  Topics: EDA - DFT  |  Tags: , ,   |  Organizations: ,
October 21, 2015

FPGA-based prototyping 3: Which board do I need?

Part three of our series looks at the choices you face as you decide whether to build or buy a board.
October 19, 2015
Nasib Naser is senior staff corporate applications engineer in the verification group for Synopsys.

Ten key tips for effective memory verification

Verification IP can help verify that memory-controller implementations meet standards; test an implementation against specific memories; and drive traffic for SoC verification and power analysis. Here's how to choose it.
Expert Insight  |  Topics: IP - Selection, EDA - Verification  |  Tags: , , , , ,   |  Organizations:

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