Guides - Tech Design Forum Techniques

September 6, 2013

On-chip variation (OCV)

Accounting for on-chip variation (OCV) has become a critical factor in assuring timing closure for nanometer-scale ICs and avoiding over-pessimistic margins.
Guide  |  Topics: EDA - Verification  |  Tags: , , , , , ,
June 2, 2013

IEEE 1801-2013 (UPF 2.1)

IEEE 1801-2013 updates and refines the Unified Power Format for low-power VLSI design, reflecting changes in power modeling and verification.
January 23, 2013

Real-value or wreal modelling

Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.
October 3, 2012

System virtual prototyping

The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.
September 18, 2012

The Yocto Project

Yocto is a project that aims to provide the open source building blocks necessary for custom embedded Linux implementations
Guide  |  Topics: Embedded - Platforms  |  Tags: , ,
August 21, 2012

2.5D-IC, 3D-IC, and 5.5D-IC – stacked-die integration

A guide to emerging 3D integration techniques for ICs, including a look at various approaches, and some of the tools and standards issues involved.
June 4, 2012

Sleep modes

For a growing number of applications, leakage is a major component of the lifetime energy consumption of an MCU, making it essential to shut the processor core down when it is not needed. Sleep modes help control that.
June 4, 2012

Side-channel attacks

A side-channel attack is a form of reverse engineering that takes advantage of the information leakage from electronic circuitry. And it is a major risk to design security.
May 28, 2012


The value of the emulation market has almost doubled in the last four years as the technique becomes increasingly valuable to hardware/software co-verification.
May 23, 2012


VHDL is a hardware description language with rich constructs that can model complex systems. It can also be constrained for use as the starting point of an FPGA or ASIC design.
Guide  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,


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