DVCon US 2018 preview: Mentor

By TDF Editor |  No Comments  |  Posted: February 12, 2018
Topics/Categories: Blog - EDA, - Verification  |  Tags: , , , , ,  | Organizations: , , ,

DVCon US runs from February 26 to March 1 2018 at the Doubletree Hotel in San Jose, California. Mentor, a Siemens business, has lined up a wide range of events during the conference, including luncheons, technical papers, panels and tutorials.

The company will be exhibiting at booth #1101 with a focus on its Catapult, PowerPro, SLEC, Questa, Veloce, and Visualizer tool suites.

The companies co-presenters in the technical section include NASA JPL, Codasip, Nokia and Northeastern University,

You can read more here and on this Mentor blog round-up.

A full list of major Mentor events at DVCon US follows:

DVCon US panel

The Right Tool (or Tools) for the Toughest Verification Tasks

Wednesday, February 28, 1:30pm – 2:30pm, Oak/Fir

Moderator: Jean-Marie Brunet, Mentor

Developments in verification front will fuel a discussion among panelists who will describe how decisions are made about which tools are implemented in a design verification flow. And how budgets are allocated. As users, they will explain why some tools dominate today’s flows and others not so much.

DVCon US sponsored luncheons

Accellera Lunch Featuring the 2018 Technical Excellence Award and Accellera Standards Activities

Monday, February 26, 12:00pm - 1:30pm, Pine/Cedar

Speakers and focus topics:

  • SystemC – Trevor Wieman, Intel & Frederic Doucet, Qualcomm
  • Verilog AMS – Scott Little, Maxim Integrated
  • SystemRDL – Steve Russell, Zyzyx
  • UVM – Justin Refice, NVidia
  • Portable Stimulus – Tom Fitzpatrick, Mentor

Validation: Verification’s Big Brother - "I Wanna Go Fast"

Wednesday, February 28, 12:00pm - 1:15pm, Pine/Cedar

Speakers: Stephen Bailey, Doug Amos (Mentor)

This ‘how to’ session will look at boosting productivity using methodologies to create environments and tests that enable the best performance from simulation, emulation and prototyping while also enabling the use of the best engines for the verification and validation objective without requiring changes to your environment and test IP.

DVCon US tutorials

Portable Test and Stimulus: The Next Level of Verification Productivity is Here

Monday, February 26, 9:00am - 12:00pm, Oak/Fir

Speakers: Tom Fitzpatrick (Mentor), Faris Khundakjie (Intel), Sharon Rosenberg (Cadence Design Systems), Adnan Hamid (Breker Verification Systems), Srivatsa Vasudevan (Synopsys), Karthick Gururaj (Vayavya Labs)

Accellera formed the Portable Stimulus Working Group to produce a standard that would allow extensive verification intent reuse. This in-depth technical tutorial considers a set of typical design use-cases and will show how to use the Portable Test and Stimulus Standard to create an abstract model of your verification intent. The tutorial will then demonstrate how these models can be used to generate scenarios to be executed on the different platforms and environments used in the development process, and how the models can be reused and leveraged from project to project.

For each application, theSpeakers will show:

  • How to model the critical verification intent.
  • How that model may be used to generate multiple compatible coverage-centered scenarios.
  • How to map that intent into multiple target-specific implementations.
  • How the declarative semantics of the model drive the generation of executable tests on different platforms to implement the desired scenarios.

IEEE-Compatible UVM Reference Implementation and Verification Components

Monday, February 26, 2:00pm - 5:00pm, Oak/Fir

Speakers: Mark Peryer (Mentor), Justin Refice (Nvidia), Mark Strickland (Cisco Systems), Uwe Simm (Cadence Design Systems), Srivatsa Vasudevan (Synopsys)

On April 11, 2017, the IEEE Standards Association (IEEE-SA) approved the IEEE 1800.2 Standard for the Universal Verification Methodology (UVM). The milestone does come with change. On one hand, there are many improvements and new features. On the other, there are changes to the both the standardized and undocumented APIs that many engineers accessed in the Accellera reference implementation to build their verification components.
This tutorial will introduce engineers to the new reference implementation aligned with IEEE 1800.2 created by the Accellera UVM WG. TheSpeakers will use the new reference implementation to describe the new features and changes relative to UVM 1.2. Engineers attending the tutorial will learn the steps they need to take to update their verification components to be IEEE-compatible. Code examples and interactive discussions with members of the Accellera UVM WG will help engineers gain the practical knowledge they need.

Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips

Thursday, March 1, 8:30am – 12:00pm, Siskiyou

Speakers: Ellie Burns, Gabriel Chidolue, Guilaume Boillet (all Mentor)

The tutorial will step through a complete low-power methodology, and explore the different types of metrics needed at different phases of the design process. It will cover a new and unique low-power coverage methodology that enables designers to verify and track how well they have tested their power management architecture. It will also show how to track not only metrics for how much power is used in the RTL, but also how much power is still being wasted and has potential to be reduced for IP qualification. Finally, it will look at how to bring real power scenarios testing into both your power measurement and management coverage metrics to provide the final phase of power verification and validation.

How to Stay Out of the News with ISO26262-Compliant Verification

Thursday, March 1, 2:00pm – 5:30pm, Siskiyou

Speakers: Doug Smith, Charles Battikha (all Mentor)

The ISO 26262 standard defines the safety level of a design via specific safety goals, safety mechanisms, and fault metrics. However, even though there are sections of ISO 26262 dedicated to electronic systems in general, and semiconductors in specific, the mapping of the specification to the implementation of design and verification best practices is not specifically delineated.

Hence, in this tutorial you will learn:

  • What are the basics of the ISO26262 standard as it applies to requirements for electronic design and verification of safety critical products.
  • How to estimate the safety level of a design by defining safety goals, selecting “safety mechanisms”, and specifying fault metrics.
  • How today’s dynamic, static, and hardware-assisted verification flows can be employed to verify the safety-critical RTL designs, gate-level implementations, and embedded bare-metal software and firmware.
  • Advanced techniques to eliminate large numbers of irrelevant faults without compromising the completeness of the verification, or the safety of the finished product.

DVCon US technical sessions

1.1 Clock Domain Crossing Challenges in Latch Based Designs

Tuesday, February 27, 9:00am - 10:30am, Oak

Speaker: Madan M. Das (Mentor). Authors: Madan M. Das, Chris Kwok, Kurt Takara (all Mentor)

1.2 Using Formal to Exhaustively Determine Unsafe Clock Ratios Between Asynchronous Blocks

Tuesday, February 27, 9:00am - 10:30am, Oak

Speaker: Eric Hendrickson (NASA’s Jet Propulsion Lab & Jet Propulsion Lab). Authors: Eric Hendrickson (NASA’s Jet Propulsion Lab & Jet Propulsion Lab), Bill Au (Mentor), Joe Hupcey III (Mentor), Richard Ilaca (Mentor)

2.2 Building Portable Stimulus Into Your IP-XACT Flow

Tuesday, February 27, 9:00am - 10:30am, Fir

Speaker: Matthew Ballance (Mentor). Authors: Petri Karppa (Nokia), Lauri Matilainen (Nokia), Matthew Ballance (Mentor)

5.1 Transparently Checkpointing Software Test Benches to Improve Productivity of SoC Verification in an Emulation Environment

Tuesday, February 27, 3:00pm - 4:30pm, Oak

Speaker: Ankit Garg (Mentor). Authors: Ankit Garg (Mentor), Suresh Krishnamurthy (Mentor), Gene Cooperman (Northeastern University), Rohan Garg (Northeastern University), Jeff Evans (Mentor), Neil Rosenberg (Intel)

5.3 UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer

Tuesday, February 27, 3:00pm - 4:30pm, Oak

Speaker: Ritesh Goel (Mentor). Authors: Marcela Zachariasova (Codasip), Lubos Moravec (Codasip), John Stickley (Mentor), Hans van der Schoot (Mentor), Shakeel Jeeawoody (Mentor)

6.2 Debugging Functional Coverage Models get the Most out of Your Cover Crosses

Tuesday, February 27, 3:00pm - 4:30pm, Fir

Speaker: Mennatallah Amer (Mentor). Authors: Mennatallah Amer (Mentor), Amr A. Hany (Mentor)

8.3 UVM and C Tests - Perfect Together

Wednesday, February 28, 10:00am -12:00pm, Oak

Speaker and author: Rich Edelman (Mentor)

12.1 Whose Fault Is It Formally? Formal Techniques for Optimizing ISO 26262 Fault Analysis

Wednesday, February 28, 3:00pm - 4:30pm, Fir

Speaker: Ping Yeung (Mentor). Authors: Ping Yeung (Mentor), Doug Smith (Mentor), Abdelouahab Ayari (Mentor)

13.1 Unveil the Mystery of Code Coverage in Low-Power Designs:Achieving Power Aware Verification Closure

Wednesday, February 28, 3:00pm - 4:30pm, Monterey/Carmel

Speaker: Madhur Bhargava (Mentor Graphics (India)). Authors: Madhur Bhargava (Mentor Graphics (India)), Durgesh Prasad (Mentor Graphics (India)), Pavan Rangudu (Mentor)

13.2 Low Power Coverage: The Missing Piece of Dynamic Simulation

Wednesday, February 28, 3:00pm - 4:30pm, Monterey/Carmel

Speaker: Progyna Khondkar (Mentor). Authors: Progyna Khondkar (Mentor), Ping Yeung (Mentor), Gabriel Chidolue (Mentor)

13.3 Low Power Apps: Shaping the Future of Low Power Verification

Wednesday, February 28, 3:00pm - 4:30pm, Monterey/Carmel

Speaker: Awashesh Kumar (Mentor Graphics (India)). Authors: Awashesh Kumar (Mentor Graphics (India)), Madhur Bhargava (Mentor Graphics (India)), Pankaj Gairola (Mentor Graphics (India)), Vinay K. Singh (Mentor Graphics (India))

DVCon US poster sessions

Tuesday, February 27, 10:30am – 12:00pm, Gateway Foyer

4.3 UVM-FM: Reusable Extension Layer for UVM to Simplify Functional Modeling

4.4 Unraveling the Complexities of Functional Coverage: An Advanced Guide to Simplify your use Model

4.7 A Specification-Driven Methodology for the Design and Verification of Reset Domain Crossing Logic

4.11 Managing and Automating Hw/Sw Tests from IP to SoC

4.12 Preventing Chip-Killing Glitches on CDC Paths with Automated Formal Analysis

4.14 Reusable UPF: Transitioning from RTL to Gate Level Verification

4.15 Hybrid Approach to Testbench and Software Driven Verification on Emulation

4.20 SoC Verification of Analog IP Integration through Automated, Formal-based, Rule-driven Spec Generation

4.26 Tired of Slow Gate Level Design Verification? Use these Efficient Modelling Styles and Methodology

4.29 Comprehensive IP to SoC Clock Domain Crossing Verification Using Hybrid Data Model

4.30 Cleaning Out Your Pipes - Pipeline Debug in UVM Testbenches

4.31 Improving Verification Predictability and Efficiency Using Big Data


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