Circuit noise problems can originate from a variety of sources. By carefully examining attributes of the offending noise you can identify it’s source, thereby making noise reduction solutions become more apparent. There are three subcategories of noise problems: device, conducted and radiated noise. If an active or passive device is the major noise contributor, you […]
The article describes how a methodology based around scalable transaction level modeling (TLM) techniques can be used to enable software design to begin far earlier in a design fl ow and thus allow companies to bring designs to market faster, particularly in time-sensitive sectors. It is based on the creation of high-level hardware models that […]
The article describes a dedicated low-power functional verification methodology, originally developed at STMicroelectronics (now ST-Ericsson). The article details the content, sequence and effectiveness of the methodology as it was tested on a 45nm system-on-chip design. In order of use, the main components are: A high-level verification language testbench Formal verification Rule checking C function library […]
The article describes the context and need for embedded operating systems that are more responsive to the power management demands placed on today’s electronic devices. It reviews the design objectives for the two main types of power management, reactive and proactive, and examines how both can be implemented. For decades, scientists and engineers have been […]
Since 130nm, you have either had an innovative approach to low-power design, or you have not had a business. From that node onwards, low-power requirements began to match raw performance in driving the R&D agenda. Where the cutting edge was once defined by communications infrastructure and programmable logic, consumer electronics (CE) started to become ever […]
Traditional verification tools struggle to deal with today’s increasingly sophisticated power management technologies. One major limitation is that they cannot deal with varying power states because they make a built-in assumption that devices are always fully powered on. Further, power-aware verification at the register-transfer level is proving increasingly problematic, although it is also becoming increasingly […]
The architectures that underpin today’s traditional place-and-route tools are showing their age, largely because their static timing analysis engines cannot handle more than two mode/corner scenarios. Thus limited, the software struggles to effectively implement low-power design techniques beyond such established concepts as clock gating and multiple threshold voltages. Designers run into difficulties when trying to […]
Today’s system-on-chip designs often need to encompass multiple asynchronous clocks. This raises the problem of verification for the resultant clock domain crossings. It is becoming apparent that functional simulation alone is not up to the task. Instead, engineers need to consider hybrid methodologies, combining structural and functional verification approaches. The use of assertions is also […]
Chemical mechanical polishing (CMP) has traditionally been considered an enabling technology. It was first used in the early 1990s for BEOL metallization to replanarize the wafer substrate thus enabling advanced lithography, which was becoming ever more sensitive to wafer surface topography. Subsequent uses of CMP included density scaling via shallow trench isolation and interconnect formation […]
The paper describes several innovative modifications to standard design flows that enable new device technologies to be rapidly assessed at the system level. Cell libraries from these rapid flows are employed by a design flow description language (PSYCHIC) for the exploration of highly speculative ‘what if’ scenarios. These rapid design flows are used to explore […]
