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By Kevin Meyer |  No Comments  |  Posted: May 1, 2009
Topics/Categories: EDA - DFM  |  Tags: ,

Since 130nm, you have either had an innovative approach to low-power design, or you have not had a business. From that node onwards, low-power requirements began to match raw performance in driving the R&D agenda. Where the cutting edge was once defined by communications infrastructure and programmable logic, consumer electronics (CE) started to become ever more important. And what has gone for design has inevitably gone for manufacturing also.

The CE companies require silicon that allows their products—particularly today’s plethora of portable devices—to offer continuously improving battery life and progressively expanding functionality. Meanwhile, there are growing issues surrounding both active and standby power consumption—some requirements here may be subject to regional regulation. Electronics today have to cope with more ‘vampires’ than even the heroine of a teenage novel.

All this implies the need for a delicate and carefully engineered balance between power and performance. At the same time, these twin masters must be served at the lowest possible cost, given CE’s thin end-product margins.

Obvious economic tensions have threatened to rise to unbearable levels as the 32nm node has loomed. Existing technology (particularly the use of polysilicon-oxynitride as a gate material) is proving almost impossible to scale cost-effectively—indeed, associated leakage currents rise as processes shrink. Meanwhile, the massive investments required to introduce viable alternatives and build out manufacturing capacity would appear to be completely at odds with the cost controls demanded by CE companies.

There is an answer, and it lies in open and easy access to the latest innovations as they are developed through a broadly representative collaborative model. Our company, Chartered Semiconductor Manufacturing, is part of such a model at two levels.


First, Chartered is a member of the well-established Common Platform technology alliance with IBM and Samsung Electronics, offering foundry access to bulk CMOS 32/28nm, 45nm, 65nm and 90nm process technologies, and incorporating industry innovations such as high-k, metal-gate (HKMG) technology, 193nm immersion lithography and ultra-low-k dielectrics. Three foundries—one process.

Common Platform technology also provides access to a full suite of tools and an IP ecosystem. For low power, this was recently boosted by a joint implementation agreement with ARM, the leading supplier of physical IP (libraries, memories and I/Os) as well as the dominant microprocessor architecture and embedded core provider for mobile devices. This agreement specifically addresses the development of energy-efficient devices at the 32nm and 28nm nodes.

Second, all the Common Platform members are also part of the Joint Development Alliance (JDA), a still wider collaboration on the development of future manufacturing processes. As other such alliances have disbanded or fallen away, the JDA has grown and grown to the point that it now also includes Infineon Technologies, STMicroelectronics, Global Foundries (the spin-out from AMD), Toshiba and NEC as well as the Common Platform partners Chartered, IBM and Samsung.

The JDA has the global reach to move new technologies quickly into the mainstream and, perhaps more important, the combined resources to undertake the capital-intensive R&D needed to take semiconductor process development and manufacturing into the future. Certainly, what Chartered offers at 32nm this year and 28nm next year by virtue of its Common Platform membership would have otherwise been unthinkable.

Toward 32/28nm

As noted, a simple PolySiON shrink for the 32 or 28nm nodes could offer little advantage to the end device—perhaps no more than an ability to put more die on a wafer, once various trade-offs have been accounted for. Indeed, given issues at 32 or 28nm related to rises in leakage current, transistor variation and threshold voltage mismatches, the resulting silicon could even be worse in terms of power and performance than that produced at an earlier generation.

The industry has already introduced a number of techniques to mitigate the problems posed by progressive sub-micron nodes (e.g., voltage islands, strain, etc.). However, at 32 and 28nm, the physical inability to scale traditional gate oxide any further on a viable basis has become the primary challenge.

The obstacles presented by each successive geometry are causing more companies to ask themselves if it is worth the additional design effort and associated cost of moving forward as new nodes, leveraging material science innovation, become available. In some cases, holding back and better leveraging existing design platform investments may well be the best option, but the technology drivers identified earlier mean that some markets still need to advance. Moreover, continuing to innovate and match the demands of Moore’s Law is not just technologically, but also economically fundamental to the growth of the semiconductor industry.

Since the 45nm node, the combination of a high-k dielectric with metal gates has become an essential part of the process recipe for achieving these goals. It is not a technology that was immediately open to everyone, although through the Common Platform alliance, it now can be.


The replacement of silicon dioxide with appropriate materials (typically hafnium-based) that have a high dielectric constant (k) has allowed us to shrink gate equivalent oxide thickness at 32nm from 18Å to just 10Å (1nm). At the same time, gate leakage is reduced by 10X.

When this is coupled with the implementation of a ‘gate-first’ metal gate technology, the combination offers a 40% reduction in power and a 20% increase in performance with Vdd at 1V.

A further benefit comes in a reduction of mask costs compared with those necessary for the implementation of, typically, stress engineering—where separate masks might be required for each type of stress applied to different parts of the design. Then, one sees less transistor variation and better threshold voltage mismatches.

To a CE industry beset by the need to advance power and performance while extending battery life and controlling cost, this combination of qualities appears made to order. HKMG is not so much a game changer, as a technology that keeps the industry in the game. But who has been able to afford it?

Intel, not surprisingly, has an HKMG strategy that began rolling out across its 45nm microprocessor implementations (and which differs from that offered by Chartered and its partners by, for example, using a more performance-biased, gate-last manufacturing flow). Meanwhile, the HKMG technology available through the Common Platform was largely an IBM-led innovation in material science over the past 10 years.

What these companies have in common is that both had the resources and the vision to undertake the necessary research into architecture, process flow and material science needed to make HKMG a reality for 32 and 28nm systems-on-chip (SoC). They also have the internal structures whereby both their process engineering and chip design teams are natural contributors to any manufacturing development process, and consequently every step is taken with the designer in mind. Finally, HKMG research has been under way at both companies for at least a decade. Think about that for a moment—think of it as a commitment to innovation in terms of both time and money.

However, for the mainstream market, the big differentiator with the IBM-led HKMG joint technology development is its availability to all, not just to serve one set of internal goals, nor just those of the JDA companies. Through the Common Platform, any fabless or fab-lite semiconductor company (or, indeed, any transitioning IDM) can realistically look to take advantage of the lower power and the higher performance offered by HKMG in its next-generation designs.

For us, this availability is a validation of the shared technology model—it brings the latest innovations swiftly to the mainstream design market. For our customers, it is pure competitive advantage, the chance to meet the demands placed on today’s products by using the latest technology, and doing so within an infrastructure that will smooth the implementation.

Chartered is already offering HKMG on multi-project wafers for prototyping. Volume production is then expected to start ramping before the end of 2010. As the saying goes, the future is available today.

Kevin Meyer is vice president, Industry Marketing & Platform Alliances at Chartered Semiconductor Manufacturing, and Dr. J.C. Young is senior manager, field technical specialist with the company. More details on working with and benefiting from HKMG for low power and other applications are available at

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