EDA Topics

Using formal property verification to prove that SoCs can’t do the wrong thing, as well as that they will do the right thing.

Dr Walden Rhines, chairman and CEO of Mentor Graphics, opens a two-part analysis by looking back at the dominant design and business trends in 2015.

The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.

Behind the drivers for memory BIST innovation in areas such as power-on self-test, destructive and non-destructive techniques, and faster memory repair.

Traditional approaches do not catch all unknown state sources, lack capacity for big SoCs and mask bugs. Ascent XV addresses and overcomes these issues.

More protocols, multibillion-gate designs, minimized power, burgeoning software and, for networking, hundreds of switch and router ports emphasize the need for scalable, virtualized emulation.

How parallelism in project management, synthesis and processing resources can accelerate FPGA-based design

The arrival of the 10nm process will impact the way that designers approach custom and mixed-signal layout. Cadence Design Systems has made changes to its Virtuoso environment that deploy increased automation support and electrically-aware layout to deal with the upcoming issues.

How AMD coupled a virtual PC and transaction-based emulation to accelerate the verification of its latest GPU

How to save test time and test costs by doing more tests in parallel, increasing compression, pooling tester memory, managing branching - and more