How to maximize productivity with faster, high-capacity RTL synthesis

Synthesizing RTL for large SoCs at advanced nodes is fraught with challenges that stifle productivity. For better design flow efficiency, quality of results, and turnaround time, engineers need a high-capacity RTL synthesis tool that can optimize at a higher level of abstraction, not at the gate level.

RTL synthesis has historically placed greater emphasis on gate-level optimization. Yet such optimization faces capacity limitations and long runtimes.

By contrast, synthesis at higher levels of abstraction offers such benefits as:

• Faster runtimes.
• More opportunities for improvements to QoR, pin placements, feedthroughs, and timing.
• Greater tool capacity.

Overcoming historical synthesis inefficiencies

When capacity is limited, projects must be split into smaller blocks for synthesis that are later stitched back together for physical design. Breaking designs into blocks that do not correspond to the physical hierarchy is asking for trouble. It is very difficult to get a good partition, and hard to budget timing constraints across the blocks.

The biggest problem with a block‐level synthesis approach manifests itself as endless iterations when assumptions made by the synthesis tool, which sees only a single block at a time, are invalidated by the physical design tool, which considers all the blocks as a group. The design that emerges from place and route (P&R) no longer satisfies the constraints. This results in a miscorrelation between front- end and back-end design flows.

Newer RTL synthesis tools, like Oasys-RTL from Mentor Graphics, have been architected to meet the needs of complex, advanced-node, high-performance designs largely by enabling and exploiting the benefits of abstraction.

Abstracting RTL synthesis

Formerly called RealTime Designer, Oasys-RTL uses a patented synthesis technology, ‘PlaceFirst’. This allows it to perform placement before synthesis, so high‐level optimization can be performed at the RTL level instead of the gate level.

Physical RTL synthesis PlaceFirst technology works by partitioning the RTL into placeable partitions, and then refining those down into actual library cells so that physical placement information is available at all times. A detailed netlist of each RTL partition is also available and is used to accurately time the design. The placement and timing information is dynamically updated with every optimization transform.

PlaceFirst reduces the number of objects to be handled during synthesis. This helps give it the capacity to handle 100+ million gates in up to 10X shorter runtimes while maintaining tight correlation with Mentor’s place and route tool on wirelength and timing.

Figure 1. Optimizing at the RTL level offers more room for QoR improvement, higher capacity and faster runtimes (Mentor Graphics)

The results allow designers to reduce an entire chip from RTL to placed gates very quickly.

In Oasys-RTL, the designer loads the entire design, and the tool automatically creates a floorplan based on the high-level RTL modules and design data flow. High-level modules in the input RTL are assigned to regions as constrained by the floorplan, and then the whole RTL is partitioned. The original RTL partitions are re-synthesized with their physical and timing constraints to optimize the design.

The partitions are then refined down into actual library cells so that physical placement information is available at all times. This fast constraint-driven synthesis of RTL directly to library cells is a second patented breakthrough technology in Mentor’s synthesis tool. The result is faster design convergence and better QoR.

In the final refinement step, all the gates are legally placed and the design is fed forward ready for P&R.

Designers can also create a production-ready floorplan in the synthesis tool, even performing quick what-if analysis to compare different scenarios. Since real physical implementation and delays are factored during synthesis, this results in a reliable and predictable design flow. It reduces the time needed to generate a production-quality floorplan to a matter of days.

Another way next-generation RTL synthesis can boost design productivity is by providing full cross-probing capabilities between the physical and RTL databases. These let RTL engineers quickly find the root causes of timing and congestion issues and resolve related problems early in the design cycle. Mentor’s tool is the first to provide all the design views, from logical to physical to timing, in a single RTL synthesis platform.

Figure 2. Oasys-RTL is the first RTL synthesis tool to provide all the design views in a single database (Mentor Graphics)

Because of its unique architecture and patented technologies, Mentor’s tool can perform RTL synthesis significantly faster than those based on a conventional flows. Oasys-RTL delivers equal or better quality of results (Table 1), and placement that runs more smoothly through industry-standard P&R tools. It has the capacity to handle full‐chip designs of up to 100 million gates and a compact memory footprint.

Table 1. Comparison of Oasys-RTL and conventional logic synthesis flows on two designs (Mentor Graphics).

Further reading

To learn more about the next generation features enabling RTL synthesis for advanced nodes using Oasys-RTL, you can also download this white paper.

About the author

Arvind Narayanan ​is a Product Marketing Manager at Mentor Graphics. He holds a Masters in EE from Mississippi State University and a Masters in Business Administration from Duke University.