timing closure

January 4, 2016
Interconnect variation in SoC

Timing analysis shifts to statistical

The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
April 22, 2014

Accelerating multi-corner multi-mode sign-off using the Lynx Design System

Mixed-signal chip designer Semtech on using Lynx Design System to manage multi-corner multi-mode sign-off when you've got 306 scenarios to check.
Article  |  Topics: IP - Design Management, EDA - Verification  |  Tags: , , , ,   |  Organizations:
March 27, 2014
Achieving multi-scenario signoff more quickly and predictably using timing-driven ECO

Achieving multi-scenario signoff quickly and predictably using timing-driven ECO

Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , ,   |  Organizations:
December 23, 2013
Featured image Marvell case study

Better management of timing closure and optimization

How Marvell used an enhanced ECO tool flow for SoC design to cut overall time-to-timing-closure by nearly 70%.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , ,   |  Organizations: ,

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