formal verification

High-level synthesis provides a way to explore hardware architectures to come up with the most efficient implementation for a given situation. But it has taken time for verification techniques to catch up with the idea and ensure design and architecture match.

Considering design style, assertions, engines and coverage can help ease the development of an effective formal verification test plan

A look at three techniques to verify the validity of signals moving between clock domains

Constraints are a vital part of IC design, yet the management and verification of constraints’ quality, completeness, consistency and fidelity to the designer’s intent is an evolving art.

Formal techniques can be applied to various parts of the verification challenge, including low-power and clock domain-crossing issues

The ISO 26262 safety standard lays out a number of best practices for the automotive industry and for suppliers. Formal verification provides a way of streamlining the verification of SoCs that need to conform to the standard.

The argument for an integrated approach to SoC verification

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.

As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.

Verification coverage attempts to at least provide a partial answer to the question: "How do you know you are finished verifying?" It involves the combination of a number of techniques.