Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.
To check the connectivity of an SoC, first you have to define what a connection is...
Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.
A look at how formal verification strategies can be used to check the security feature of complex SoCs for potential data leakage and data integrity issues
Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.
Bus contention and floating busses are well defined issues and therefore excellent candidates for being addressed with early-stage formal verification.
Finite State Machines are such a familiar part of design, we can forget how often they generate errors. Learn how to address them quickly and most efficiently
High-level synthesis provides a way to explore hardware architectures to come up with the most efficient implementation for a given situation. But it has taken time for verification techniques to catch up with the idea and ensure design and architecture match.
Considering design style, assertions, engines and coverage can help ease the development of an effective formal verification test plan
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