formal verification

May 22, 2017
Ashish Darbari is CEO of formal verification consultancy Axiomise.

Introducing Doc Formal: the journey so far

Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
February 23, 2017
Cache verification involves checking multiple scenarios

Cache-coherency checks call on portable stimulus

Portable stimulus and formal verification provide the means to handle the challenge of verifying cache-coherent SoC interconnects.
January 18, 2017
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Are you formally connected?

To check the connectivity of an SoC, first you have to define what a connection is...
Expert Insight  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: ,   |  Organizations:
August 28, 2016
Chips on a wafer

Addressing the verification challenges of complex SoCs

Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.
July 5, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Are you formally secure?

A look at how formal verification strategies can be used to check the security feature of complex SoCs for potential data leakage and data integrity issues
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
May 30, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Comparing your design to itself – a crucial part of verification

Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.
January 26, 2016
Bus contention and floating bus issues featured image

Bus contention and floating busses: Catch them before simulation

Bus contention and floating busses are well defined issues and therefore excellent candidates for being addressed with early-stage formal verification.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:
January 18, 2016
How to debug and verify finite state machines early in the design flow

Finite state machines: How to debug and verify them early in the flow

Finite State Machines are such a familiar part of design, we can forget how often they generate errors. Learn how to address them quickly and most efficiently
Article  |  Topics: EDA - Verification  |  Tags: , , , , ,   |  Organizations:
September 24, 2015
OneSpin HLS and formal verification

Linking high-level synthesis with formal verification

High-level synthesis provides a way to explore hardware architectures to come up with the most efficient implementation for a given situation. But it has taken time for verification techniques to catch up with the idea and ensure design and architecture match.
June 30, 2015
Mark Handover is an applications engineer with Mentor Graphics

Back to basics – doing formal the right way

Considering design style, assertions, engines and coverage can help ease the development of an effective formal verification test plan
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:

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