formal verification

Accellera's Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.

As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.

Verification coverage attempts to at least provide a partial answer to the question: "How do you know you are finished verifying?" It involves the combination of a number of techniques.

X propagation within RTL simulations can hide fatal bugs. Uncovering and eliminating the effect improves design quality and avoids respins.