EDA

Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.

Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’

Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.

A look under the hood of IC Compiler II, Synopsys' next-generation netlist-to-GDSII implementation system.

This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.

This article looks at some of the key architectural and implementation decisions Synopsys has made in developing a version of its HS series of licensable processor cores to serve the embedded Linux market

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.

A look at a tool and a flow that makes it easier to put designs on to a HAPS physical prototyping system for verification, debug and software development purposes

FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.

Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.