clock gating

November 6, 2017

Using sequential equivalence to verify clock-gating strategies

Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques such as clock gating or register re-timing.
Article  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
May 30, 2016
Anders Nordstrom, senior corporate applications engineer, Verification Group, Synopsys

Comparing your design to itself – a crucial part of verification

Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.
May 31, 2015

Technology trends demand netlist-level CDC verification

Complex processes and aggressive synthesis interventions are increasing the risks of metastability, creating a need for netlist-level CDC verification
May 7, 2013
Graham Bell, RealIntent

Better analysis helps improve design quality

Better upfront analysis can help avoid propagating errors from RTL into the netlist, and reveal a number of ways to improve the quality of your final design.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
April 9, 2013

How AMD implemented efficient clock gating analysis for Jaguar

The chipmaker used Calypto’s PowerPro to carry out power analysis of its latest core design at the RTL rather than at post-gate synthesis.
Article  |  Topics: EDA Topics, EDA - IC Implementation  |  Tags: , , ,   |  Organizations: , ,
March 11, 2013
Metastability at clock boundary

Clock-domain and reset verification in the low-power design era

The multiple clock domains on today's SoCs create a hotbed for clock-domain crossing bugs to thrive. Low-power design techniques increase the complexity of tracking these bugs down. Find out how these failures arise and what to do about them.
Article  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
August 23, 2012
Pranav Ashar

Verification challenges require surgical precision

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations:

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