Cadence Design Systems

July 26, 2012
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Optimizing cloud computing for faster semiconductor design

How Cadence, Intel and Xuropa accelerated the semiconductor design process by squeezing 15% more capacity out of a virtualized server farm
August 23, 2011
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The Universal Verification Methodology: ready, set, deploy

Mentor’s Dennis Brophy, Cadence’s Stan Krolikoski and Synopsys’ Yatin Trivedi describe how you can prepare to adopt Accellera’s Universal Verification Methodology.
Article  |  Topics: EDA - ESL  |  Tags: , ,   |  Organizations: , ,
December 1, 2008

No double-quick growth for DDR3

Lane Mason Marc Greenberg DDR3 DRAMs still languish around the edges of the market despite their supposed attraction in terms of power and performance, the widespread availability of product, and the presence of a supposedly ‘evolved’ ecosystem and implementation infrastructure. Just over 18 months ago, Intel launched a major Go To DDR3 market initiative at […]

Article  |  Topics: Embedded - Platforms  |  Tags: , ,   |  Organizations:
December 1, 2007

Mastering the memory maze

Since the early 1980s,most of the semiconductor business has been enthralled by the microprocessor, the PC and commodity DRAMs. For all the talk of potential ‘better markets’ and ‘more profitable businesses to be in’, PCs and their brethren came to represent 35- 40% of the industry’s output. They constituted the prime platform for not only […]

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