power analysis


November 6, 2023

Cadence combines ML techniques for power signoff

Cadence has linked several machine-learning approaches to build a tool that is designed to speed up the detection and diagnosis of on-chip power-integrity issues.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
June 16, 2017

DAC 2017 preview: Baum

Start-up Baum is co-located with Verific at DAC 2017 and will demonstrate its soon-to-launch power analysis and modeling software.
Article  |  Topics: Blog Topics, Conferences, Blog - EDA, - Product, RTL  |  Tags: ,   |  Organizations: , ,
December 22, 2016

Webinar discusses SoC security, area, and power trade-offs

SoC security strategies, costs and trade-offs are analysed in this detailed webinar.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:

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