Constrained random testbenches excel at quickly hitting the majority of coverage but their effectiveness trails off as coverage closure nears completion. This paper describes a testbench API that sits on top of OVM sequences allowing the existing constrained random infrastructure to be guided, enabling faster, more efficient coverage closure. Design and verification engineers can use [...]
Morris Chang was in on the ground floor of IC innovation at TI and remains there today as chairman of TSMC. Paul Dempsey reports.
John Landau According to analysts at Screen Digest, revenue from 3D theatrical releases in North America reached $1.1bn in the first six months of 2010. This was the first time that the half-year number had exceeded the billion-dollar mark and was more than double the $430m in 3D ticket sales for the same period in […]
FPGA-based signal processing has traditionally been implemented using fixed-point operations, but high-performance floating-point signal processing can now be implemented. This paper describes how floating-point technology for FPGAs can deliver processing rates of one tril- lion floating-point operations per second (teraflops) on a single die.
Sematech, the leading research consortium for semiconductor manufacturing, has launched a campaign to recruit members from the fabless sector. The move reflects the importance of making manufacturing decisions earlier in the design flow, and is also intended to get input from designers on implementations of such technologies as 3D interconnects, next-generation lithography and novel materials/structures.
Characterizing PLL jitter is important yet challenging. Usually done through transistor-level transient analysis, a slow simulation speed has been the major bottleneck preventing jitter from being characterized in a timely manner. This paper presents an approach for fast jitter characterization using mixed-signal simulation (a combination of transistor-level blocks and calibrated behavioral models). Among various PLL [...]
Assertions and assertion-based verification (ABV) are hot topics, but many engineering teams remain unfamiliar with the benefits they bring to the design and verification process. This article discusses the rationale behind them, the value they bring across the design and verification process, and offers a step-by-step approach to implementing them.
This paper describes Medea, a NoC-based framework that uses a hybrid shared-memory/message-passing approach. It has been modeled in a fast, cycle-accurate SystemC implementation enabling rapid system exploration while varying several parameters such as the number and type of cores, cache size and policy, and specific NoC features. Also, each SystemC block has its RTL counterpart [...]
Danish life science entrepreneur Medotech needed a way to provide secure and simple access to its Grindcare medical devices deployed on patients’ home networks. This article outlines how Medotech solved the problem using Nabto’s patented off-the-shelf embedded software and describes how the implementation simplifies system maintenance and future development. A further section considers the integration [...]
How fares the M&A market? Despite the recent recession, deals still got done. Indeed, downturns mean bargains for those who have husbanded their resources well, and all of EDA’s leading companies were active. Nevertheless, some questions remain. At one level, there is the infamous tale about a meeting of business angels who were accused of […]