Volumes

August 23, 2011

Combining algebraic constraints with graph-based intelligent testbench automation

The description of the stimulus to a device-under-test is becoming ever more complex. Complex constraint relationships need to be defined, and the use of randomly generated stimulus to achieve comprehensive coverage metrics is proving less predictable and more labor-intensive. Using the combination of a graph-based stimulus description with a more intelligent algebraic constraint solver, a [...]
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June 3, 2011

This one now goes to 12

We quiz TSMC’s Tom Quan on the latest methodological challenges being addressed by the world’s largest foundry’s signature Reference Flow.
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June 2, 2011

Efficient RC power grid verification using node elimination

To ensure the robustness of an integrated circuit, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has been done to develop Model Order [...]
June 2, 2011

Creating a rugged standard for embedded memory

Most memory module standards have not been specified with particular reference to extreme environments where shock and vibration may present significant risk. Rather, designers have had to use a number of workaround techniques, strapping or even directly soldering devices to the board. In addition, the drive toward smaller board sizes is presenting a number of [...]
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June 2, 2011

Strategic considerations for emerging SoC FPGAs

This white paper describes the emergence of SoC FPGAs, the drivers behind their market, and proposes some strategic considerations for executive management and system designers when choosing these devices.
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June 2, 2011

DRC+: a pattern-based approach to physical verification

DRC+ is a new methodology that algorithmically characterizes design variation through pattern classification. A traditional design rule is used to identify all design structures that share a common configuration. Then, the 2D geometric situations (pattern variations) around the configuration are extracted and classified. Since all such classes share a common configuration, each situation class represents [...]
June 1, 2011

The challenge of analog, mixed-signal and custom physical implementation at 28nm

The 28nm process node has once more raised the design bar in terms of the DFM checks needed to realize a design. This is particularly true for analog and mixed-signal engineering, where rules that could once be maintained manually now need to be addressed in a more integrated, automated, and timely way. The article explores [...]
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June 1, 2011

NoC-MPU: a secure architecture for flexible co-hosting on shared memory MPSoCs

Data protection has long been a major issue for embedded systems, but it is becoming even more challenging with increasing adoption of multicore technology.
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June 1, 2011

Opening up the dialogue

A bid for more interactivity is one of the program cornerstones for the 48th Design Automation Conference.
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June 1, 2011

Balancing devices and manufacturing

Fab owners are looking to bring down their energy consumption to match the greening of semiconductors themselves.
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