Andre Geim When you were young, did you enjoy bouncing around on a trampoline? If so, try this for size. Imagine a membrane about 275 miles long, one mile deep and an average of 10 miles wide. These dimensions matter. Because this sheet of material covers the entire Grand Canyon—and before you go bouncing on […]
Lane Mason Marc Greenberg DDR3 DRAMs still languish around the edges of the market despite their supposed attraction in terms of power and performance, the widespread availability of product, and the presence of a supposedly ‘evolved’ ecosystem and implementation infrastructure. Just over 18 months ago, Intel launched a major Go To DDR3 market initiative at […]
Guy Haas Managing EDA software involves more than monitoring and studying usage across various tools and features. An effective approach will help the enterprise reduce engineering software costs, reach better and more informed business decisions, become more responsive and ensure compliance with software licenses. To understand how to develop such strategies, we need to look […]
Richard Goering System-on-chip designers who work with third-party silicon intellectual property (IP) will see some significant changes at 32nm and below. Physical IP will be highly optimized to specific processes, following intense collaborations between large IP providers and foundries. Processor IP may become less synthesizable and make more use of hard macros. On the plus […]
The Oasis file format is intended as the long-term successor to GDSII, which is now 30 years old. However, even though the first specification for Oasis was released in 2004, there is still a great deal of confusion and ignorance surrounding the standard. The article looks at the background of Oasis’ development, identifies its strengths […]
This special edition of EDA Tech Forum Journal concentrates on PCB design. It’s an exciting area technologically right now, and we hope that the editorial content reflects that. One theme that kept emerging was that many of the contributors believe their discipline is at some sort of tipping point. And these changes don’t just come […]
Floorplanning informed by thermal analysis can significantly improve PCB layouts, writes Robin Bornoff The number of PCB design constraints seems ever increasing. The risk that a design will fail either functional performance or reliability goals grows for each generation. One increasingly popular trade-off addresses a balance between thermal compliance and signal integrity. Components with high […]
This paper builds on “Timing Numbers In ICX – What do we do with them?” [1]—a paper presented at the 2006 Mentor Graphics User2User conference (and now available for download at the journal’s Web site, www.edatechforum.com). The original paper focused on the need for timing analysis and the theory behind it; this paper takes a […]
What impact do HDI via structures have on PCB design metrics? Andy Kowalewski describes a recent experiment. A PCB’s density has traditionally been seen as a function of the trace and space geometry and the number of signal layers. Emerging technologies such as microvias and buildup fabrication may force us to rethink this formula. In […]
OSMOSIS is a super-fast optical switch developed through the Advanced Simulation and Computing program. The article describes the strategies adopted by the IBM team charged with designing the Central Scheduler board for the project. The design was of a far greater complexity than the team had previously encountered, and as a result, developed new pre-preparation […]
