IP Topics

Using a hardware root of trust and a secure development lifecycle process to form the basis of a better approach to developing and implementing more secure complex SoCs.

Portable Stimulus allows reuse along horizontal, vertical and technique axes, but you need to be aware of the strengths and weaknesses of each to get the greatest benefits.

This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.

The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.

SoC suppliers building the key components for hyperscale data centres need access to the latest IP to handle functions such as PCIe, DDR5, cache coherency, NVMe SSDs, and the highest-bandwidth Ethernet implementations.

Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.

Application-specific processors can provide high performance for specialised tasks at low energy cost.

Optimizing the way in which machine learning algorithms are implemented in hardware will be a major differentiator for SoCs, especially for edge devices.

Antifuse-based OTP NVM is highly scalable, has the area efficiency to enable macros  of megabit capacities, and offers low read power.

The basics of USB 3.2, how to implement it in an SoC, and how USB Type-C connectors and cables are used in USB 3.2 systems.