IP Topics

September 11, 2019

Introducing the Compute Express Link (CXL) standard: the hardware

A guide to the emerging Compute Express Link (CXL) standard, which links CPUs and accelerators in heterogenous computing environments.
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September 3, 2019

Ensuring system-level security of complex SoCs

Using a hardware root of trust and a secure development lifecycle process to form the basis of a better approach to developing and implementing more secure complex SoCs.
April 26, 2019
Portable Stimulus - Three Axes of reuse - Featured Image

Focus your use of Portable Stimulus on three key axes

Portable Stimulus allows reuse along horizontal, vertical and technique axes, but you need to be aware of the strengths and weaknesses of each to get the greatest benefits.
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April 3, 2019

Understanding DDR SDRAM memory choices

This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.
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March 26, 2019

High-level synthesis for AI: Part One

The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
March 19, 2019

Using advanced IP to build SoCs for hyperscale data centres

SoC suppliers building the key components for hyperscale data centres need access to the latest IP to handle functions such as PCIe, DDR5, cache coherency, NVMe SSDs, and the highest-bandwidth Ethernet implementations.
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March 15, 2019

Enabling the move to a system-centric view

Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
March 1, 2019

Accelerating the implementation of application-specific processors

Application-specific processors can provide high performance for specialised tasks at low energy cost.
January 25, 2019

Optimizing the hardware implementation of machine learning algorithms

Optimizing the way in which machine learning algorithms are implemented in hardware will be a major differentiator for SoCs, especially for edge devices.
December 14, 2018

The antifuse advantage for one-time programmable non-volatile memory

Antifuse-based OTP NVM is highly scalable, has the area efficiency to enable macros  of megabit capacities, and offers low read power.
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