SoC
Improving SoC productivity through automatic design rule waiver processing for legacy IP
The Shift Left: how virtual prototyping reduces risk
Emulation delivers system-level power verification
Decoupled constraint modelling – a design methodology for hard real-time systems on chip
Addressing SoC performance challenges in advanced deep-submicron CMOS processes
Strategic considerations for emerging SoC FPGAs
Part 4- Power management in OCP-IP 3.0
According to Moore’s Law, system-on-chips (SoCs) should continually become more complex and integrate more components, enabled by each reduction in silicon technologies. However, power consumption does not follow the linear path implied here due to increasing leakage in deep sub-micron technologies. Hence, new power management techniques are needed to reduce power dissipation as much as […]
Stepping up
During the CEO Panel at this year’s Design Automation Conference, the men leading the three largest EDA vendors stressed that their industry can do well in a slump because it both contributes to the ongoing battle against technological limits, and enables the delivery of ever greater efficiency. But another, parallel question raised by this year’s […]
A pulsed UWB receiver SoC for insect motion control
The article describes the context and need for embedded operating systems that are more responsive to the power management demands placed on today’s electronic devices. It reviews the design objectives for the two main types of power management, reactive and proactive, and examines how both can be implemented. For decades, scientists and engineers have been […]
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