Winning the power and temperature battle with ESL exploration

By Ridha Hamza |  No Comments  |  Posted: June 1, 2010
Topics/Categories: EDA - ESL  |  Tags: ,

The analysis of important power and temperature metrics for chip design is becoming increasingly inefficient when attempted at the register-transfer level. The article proposes the fundamentals of a system-level modeling strategy that will shrink design times, provide more opportunities for architectural exploration, and deliver significant power savings.

Because complexity is increasing and process nodes are shrinking, power (along with timing and area) has become a critical issue in the design flow. Most designers use point tools to estimate power usage when working at the transistor level, gate level or RTL. But at these levels, each simulation takes too long to allow reasonable exploration of different use scenarios or comparison of the impacts from different low power implementation strategies.

Battery autonomy is no longer the only driver for power management. Along with packaging and cooling costs, power consumption has become a key product differentiator.

Power and temperature are interdependent: as mobile devices integrate more features and capabilities, the more power they consume and the hotter they get. This situation is getting worse at next-generation nano-scale technology nodes where the increase in power-temperature coupling due to leakage current threatens IC reliability and increases the risk of thermal runaway. Designers have few point tools from which to choose to address this challenge, and until now, no widely available tool has been capable of analyzing both power and temperature at the system level.

Analyzing power and temperature separately late in a design cycle increases risks to reliability, development costs and time-to-market for a system-on-chip (SoC). Better, earlier power and thermal predictions help designers make devices that consumers want while working within existing and likely environmental regulations.

To address these challenges, Docea Power has developed an electronic system level (ESL) strategy. Its Aceplorer (‘Ace’ here standing for ‘abstract concept of energy’) platform (Figure 1) enables highly abstracted modeling, simulation and optimization for power and heat dissipation in electronic systems.

Figure 1
The Aceplorer platform

Moving to ESL

When modeling a platform’s or SoC’s power and thermal behavior, architects have to take into account very heterogeneous data. For a complete architecture they typically have to model not only digital blocks but also memories, analog and mixed signal blocks, packaging, and external devices such as batteries and displays. They then have to model various use cases and scenarios, as well as the impact of power reduction techniques and the embedded software as it is likely to run on the proposed hardware configuration. 

To date, designers have used spreadsheets to manage increasingly complex power and thermal information, but the technique has reached its limits in terms of capacity, development and maintenance. Spreadsheets also lack interoperability.

Simply replacing outdated spreadsheets with a new software tool will not necessarily deliver the best solution, if that tool still works at a comparatively low level of abstraction, because it therefore cannot give the user significant new advantages over the status quo.

Operating at a higher level of abstraction than RTL (Figure 2, p. 34), Aceplorer aims to give system architects a better understanding of their designs. It is our contention that predictions made and decisions taken earlier in the design flow, specifically at the ESL, can deliver power savings in the 40-70% range. This compares with potential savings of only 10-25% on power consumption for optimization at the RTL or gate-level.

Figure 2
Aceplorer flow

Aceplorer allows designers to model, simulate and optimize the dynamic power and thermal behavior of complex systems, including intellectual property (IP) and full SoCs as well as board-level and subsystem effects. It is intended for use by system and specification engineers as well as software and hardware developers and is aimed at applications in the mobile, telecommunications, gaming, automotive, consumer, medical and military spaces.

It is based on applying the ‘separation of concerns’ principle to a design’s functional description and its power/thermal behavior. Users can therefore manage power data without modifying the existing design flow.

The first step in the Docea methodology is the generation of appropriate power, thermal and system models. 

Power modeling from heterogeneous sources

The ACE power model is a common XML-based description for capturing power behavior from informal requirements, even if the sources are heterogeneous (e.g., spreadsheet, datasheet, specification, library, etc). 

Aceplorer native voltage domain modeling allows the designer to define voltage clustering and investigate various configurations and power reduction techniques such as dynamic power management (DPM) or dynamic voltage-frequency scaling (DVFS).

This modeling is well suited to describing heterogeneous entities (e.g., digital, analog, pins, power IC, discrete devices, etc), modes (e.g., functional, test) and technology processes. The circuit model reflects the hierarchy of the systems under design. This structure can be generated automatically from standards such as IP-XACT or built by hand through a graphical interface.

The ACE power model can mix components at different levels of accuracy (corresponding to different versions of one model), and it captures the interdependencies between parameters to provide more accurate and reliable figures. A common format is used to reduce errors and misunderstandings among design teams. In addition, the Aceplorer automatically generates power intents according to the Unified Power Format (UPF) standard. This allows users to settle on the power specification and manage power intents at any stage in the design flow.

Compact modeling for dynamic thermal behavior

The situation is quite different for thermal modeling. Traditional approaches entail a long and increasingly inaccurate series of iterations between the system designer and the thermal engineer. First, a design featuring the worst-case power scenario is sent to the thermal engineer. Then the thermal engineer computes the thermal results and sends them back. This laborious back-and-forth process continues until the results converge.

The Docea methodology seeks to streamline this via a one-way transfer of temperature expertise from the thermal engineer to the electronic engineer. Thermal modeling in the Aceplorer platform is based on a dynamic thermal compact model (DTCM) generated by proprietary mathematical algorithms. Package and environment thermal behaviors are represented by a network of thermal resistances and capacitances.

Docea Power offers this compact thermal modeling generation as a service, and has already worked with customers in this field to realize complex package-on-package and system-in-package designs. The output SPICE model can be used in Aceplorer for an electrothermal simulation combining power consumption and thermal behavior, or in any SPICE simulator to characterize thermal behavior for a given power profile. 

Separating the architectural structure from the application 

Once the entire system is modeled, users can launch power and/or thermal architectural exploration. Aceplorer includes a proprietary electrothermal dynamic simulator that enables power and temperature simulation. This simulator carries out static and dynamic analyses such as IR-drop, DVFS and power/temperature coupling.

Within the platform, the architectural structure description is described separately from the final application. This enables better reuse of power and thermal models and the running of multiple use cases on the same design. For example, the power consumption of a processor depends on the application under which it runs. The platform allows users to create scenarios (i.e., a timed flow-chart model of an application) from dataflow, protocol or use-case descriptions (Figure 3). A scenario can be parameterized to fit multiple use cases and mapped to various power models in order to explore low-power architectures.

Figure 3
Working with scenarios and use cases

Aceplorer supports concurrent and hierarchical scenario structures. When activity files are available, the user matches them to power state diagrams. It also supports value change dump (VCD) files generated from Virtual Platform or other EDA tools. The latest version allows users to import time accurate scenarios from a performance simulation as a VCD trace. This provides a straightforward way of, for example, verifying the impact of software on power consumption at a very early stage of a project.

Fast thermal simulation: seconds versus hours 

The DTCM approach allows designers to execute a thermal simulation in only a few seconds while controlling accuracy, compared with several hours with a finite-element method (FEM)-based thermal simulation. This allows architects to try and compare a large set of use cases to find the best trade-offs.

A user-friendly visualization toolset enables designers to display simulation results in XML, a widely used format for easy data management and file sharing via an intranet or the Internet. The interactive environment proposes many chart types to best fit user needs, including line and bar charts, X-Y and scatter plots, Gantt charts and so on. In addition to graphs of power breakdown and temperature at various granularity levels, charts specifically designed for analysis of power state behavior and statistics are available. Every graph can be exported as an image (.jpg, .png) or as a .PDF document. Users can also create their own metrics and post-processing routines to automate report generation. Exportation in CSV (comma-separated values) format is available for post-processing in tools such as Windows Excel.

Ridha Hamza is sales and marketing director at Docea Power. His has more than 12 years of experience in the EDA and MEMS industries and holds a Master’s Degree in Microelectronics from Joseph Fourier University, Grenoble, France.

Docea Power
166B, Rue du Rocher du Lorzier
Moirans 38430

T: +33 (0) 427 858 262

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