Cadence Design Systems

Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.

Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.

FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.

A coordinated design methodology fine-tunes chip-to-package PCB layout and routing that involves high-integration devices.

A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.

Wreal modeling brings fast methods for simulating mixed-signal designs into the digital environment. And tools have arrived that make it easier to incorporate existing analog IP.

Decoupling capacitor counts are increasing as PCBs deploy more advanced silicon. But you can use automated analysis to bring counts and costs under control.

Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.

Three key characteristics determine a verification platform's ability to add value to the design flow. But how they score within a project depend on how each is applied and at which point.