Volume 7

September 10, 2010

Symbolic simulation speeds timing closure

Timing closure is a key challenge for today’s complex system-on-chip designs. Static timing analysis (STA) tools automatically analyze signal paths in a design and identify timing-critical paths that limit the clock frequency that can be achieved. Paths that can never be functionally activated or that require multiple cycles for correct operation can be identified as [...]
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September 10, 2010

Parallel simulation of SystemC TLM 2.0 compliant MPSoCs

Simulation speed is a key issue for the virtual prototyping (VP) of multiprocessor system-on-chips (MPSoCs). The SystemC transaction level modeling (TLM) 2.0 scheme accelerates simulation by using interface method calls (IMC) to implement communication between hardware components. Acceleration can also be achieved using parallel simulation. Multicore workstations are moving into the computing mainstream, and symmetric [...]
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September 10, 2010

Hypervisors and the Power Architecture

The use of multicore processors is on the rise to meet inexorable demand for increasingly sophisticated functionality in embedded systems. Hardware virtualization technology provides a complementary and game-changing approach to maximizing the utility of that extra silicon horsepower. The Power Architecture has included hardware virtualization support since 2001 in its server-based instruction set architecture (ISA). [...]
September 10, 2010

Beyond the system

This issue analyzes two of the most dynamic markets in electronics: embedded systems and microelectromechanical systems (MEMS). And both articles tell a familiar tale.
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September 10, 2010

Designing a PCB for power integrity

Signal integrity (SI) issues have been around for a while, the result of ever-faster edge rates. Both SI and PI problems manifest themselves as data errors. Indeed, PI problems are often misdiagnosed as SI problems. As such, an understanding of power delivery issues is essential to the success of any board project, as is a [...]
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June 1, 2010

Energy debugging – the next step in MCU software optimization

Knowing where your application is consuming resources is a crucial step in minimizing energy usage. The article describes a toolset developed by high-profile ARM-based microcontroller (MCU) start-up Energy Micro that helps to achieve this overarching goal within the context of a parallel move to 32bit MCU resolution.
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June 1, 2010

Signoff-driven IC design

The demands of manufacturing closure at advanced process nodes make the traditional design-then-fix flow unmanageable. At 28nm and below, designers need a solution that can address manufacturing issues at any point in the design process, enabling a true correct-by-construction methodology. An effective solution must provide design-rule-check and design-for-manufacturing analysis using the actual foundry-approved signoff rules [...]
June 1, 2010

Device native debug and verification for FPGA

GateRocket's RocketDrive facilitates integration of an FPGA into an HDL simulator to provide a "native" execution of a design on its target FPGA device. The companion RocketVision tool provides software-debugging capabilities that directly identify and enable the rapid resolution of bugs. This article considers the use of these tools in a "device native" verification and [...]
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June 1, 2010

Application-specific library subsetting

The limited cell count of standard cell libraries is restricting the performance that designs can achieve without resorting to expensive and time-consuming techniques. This article describes the addition of extended cell libraries and novel synthesis tools to a traditional RTL-to-GDSII flow in a new methodology that helps to overcome this performance brake. The technique is [...]
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June 1, 2010

Winning the power and temperature battle with ESL exploration

The analysis of important power and temperature metrics for chip design is becoming increasingly inefficient when attempted at the register-transfer level. The article proposes the fundamentals of a system-level modeling strategy that will shrink design times, provide more opportunities for architectural exploration, and deliver significant power savings.
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