Volume 7

System Modeling Language (SysML) is a Unified Modeling Language (UML) profile that allows the creation of standard descriptions of a system. However, this profile is too generic to address embedded and real-time system design. The Modeling and Analysis for Real-Time and Embedded Systems (MARTE) UML profile attempts to fill this gap by providing elements from [...]

Product engineering services can be efficiently outsourced and even the biggest players are doing it, says Michel Villemain

We talked to Mentor Graphics CEO Wally Rhines about the solutions that already exist to combat increasing design complexity.

Disneyland might be next door, but DAC 2010 is stressing a real-world perspective on chip design. We spoke to general chair Sachin Sapatnekar.

We look at some of the findings analyst group iSuppli had hoped to present at a recent summit before a Finnish volcano intervened.

As usual, this issue includes our regular preview of the Design Automation Conference (DAC), taking place this year in Anaheim, California (June 13-18). However, given this journal’s particular focus on practical design information, I wanted to highlight one DAC strand up front. Indeed, given that the event has taken more than its share of criticism [...]

This year's Design Automation and Test in Europe conference heard from a broad range of users and suppliers about the challenges to and solutions for getting optimal yields at advanced process nodes, particularly as the industry advances toward 22nm. This article recaps presentations by four executives at the Dresden-hosted event: Pierre Garnier of Texas Instruments, [...]

The time-dependent dielectric breakdown (TDDB) of inter-metal dielectrics on large-scale chips is becoming an increasingly important reliability issue across several semiconductor markets. This mechanism can cause early failures in use and is difficult to detect by traditional test, and hard to control by traditional reliability techniques.

Designers have been using dummy fill to address design for manufacturing for some time, but the process of simply wallpapering shapes into a design's "white space" to help it maintain planarity can no longer cope with the complex challenges presented at today's advanced process nodes. Not only is planarity harder to maintain, but there are [...]

The article offers a case study of the DFM planning and methodology applied during a shrink of Cambridge Silicon Radio's UF6000 system-on-chip from the 130nm to 65nm.