Concurrent multi-corner, multi-mode analysis and optimization is becoming increasingly necessary for sub-65nm designs. Traditional P&R tools force the designers to pick one or two mode corner scenarios due to inherent architectural limitations. As an example of the problem, a cellphone chip typically needs to be designed for 20 mode/corners scenarios. In the absence of a […]
There must be a better way to keep track of electronic engineering software licenses. EDA tools are very expensive, essential to R&D work, and must be properly maintained to ensure that commercial designs are completed on-schedule. Nevertheless, companies traditionally set aside little management time to put formal control systems in place for these assets. Consider […]
System-level architectural decisions made before any RTL code has been written have a much larger impact on overall system energy than RTL-level, gate-level, or circuit-level tweaks. The Xenergy tool from Tensilica estimates energy for a processor subsystem (processor, caches, local memories) based on the application code that will run on that subsystem. Designers can thus […]
Freescale Semiconductor manufactures some of the industry’s most widely used microcontrollers. The article describes the functionality behind the new Background Debug Module that has been developed for its 8 and 16bit MCUs. The BDM provides all that is needed to write, compile, download, in-circuit emulate and debug code, when deployed in conjunction with the well-known […]
Design for manufacturing (DFM) sign-off is a required step in most deep sub-micron technology design environments. However, there is no common methodology for DFM sign-off. We believe DFM should not only give an estimate of the yield, but should also point out where failures are most likely to occur, and where designers can improve their […]
You see, I feel a bit like Columbo. No, my raincoat is not egregiously grubby and I did recently buy a new car, but, well, “Dere’s still one thing dat bothers me.” And it’s this: where is the semiconductor industry going in terms of the placement of risk and capital in the value chain? Let […]
When I left the semiconductor industry to become an EDA Analyst, I was struck by two things. The first was the professionalism of the PR firms handling the EDA accounts. They not only did jobs that would be expected of them by silicon vendors, but also performed functions that we would consider part of a […]
Some 161 papers will feature during this year’s 44th Design Automation Conference (June 4-8) in San Diego with four strands at the forefront. System-level design (ESL), design for manufacturing/yield (DFM/DFY), low-power design and verification accounted for more than 40% of submissions this year, and the final line-up represents these topics in broadly similar proportion. For […]
Today, most SoC designs include both digital and analog components on the same chip, taking advantage of nanometer geometries. This demands that the current design flow bottleneck due to analog verifi-cation and integration is addressed in ways that enable this process to be completed both thoroughly and efficiently. SPICE simulation was accurate but slow and […]
Network-on-chip (NoC) could prove to be an effective methodology that addresses interconnect roadblocks to the development of more complex systems-on-chip. However the term covers many approaches, some of which – simple enhancement to existing bus technologies, the costly adaptation of theoretical networking concepts – fall short either in terms of performance or NREs. The article […]
