Volume 4

March 1, 2007

Re-evaluating the flow for package-aware chip design

Chip and package design are all too often still seen as separate stages in the design process. In today’s nanometer age and with the growing use of techniques such as system-in-package, this lack of integration can have catastrophic results. Package designers frequently encounter overly complex and un-routable silicon that requires multiple iterations to fix. Problems […]

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March 1, 2007

MPSoC demands system-level design automation

The relative performance of a single processor has leveled off in the last decade. Built-in instruction-level parallelism is becoming less efficient because issuing more than four instructions in parallel has little effect on most applications. Meanwhile, recent attempts to boost performance have come dangerously close to the energy/power consumption ceiling. Dedicated hardware accelerators may prove […]

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March 1, 2007

From A to B via Z

How important is it that the history of electronics is passed on from generation to generation of engineers in the ‘right’ way. OK, let’s acknowledge that, as in war, history is always dominated by the victors, not the losers. Let’s also admit that anyone with a career in this business wants its image to be […]

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March 1, 2007

Electronic system level design for embedded systems

There is a growing productivity gap in the design of embedded systems. One recent survey estimated that the number of lines of embedded code written per year is growing at a rate of 46% a year, although the number of developers available to write it is growing at only 7.5%. The problem is further compounded […]

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March 1, 2007

Double figures for DATE

DATE 07 (April 16-20) marks an important milestone for the Design Automation and Test in Europe conference as it reaches its tenth edition. As we went to press, the main technical program was still being finalized, but DATE has again received record submissions, 933 against last year’s 834. The most obvious change in 2007 is […]

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