This paper describes a random test generation strategy we are using to complement the verification of upcoming generations of processor. SystemVerilog provided the means to define the functional coverage of our design and to employ the shadow modeling technique, significantly improving our verification flow. Shadow modeling is a reliable method for proving the functionality of […]
For a design targeted at the 130nm process node or below, the cost of a dedicated mask-set is getting brutal. At 130nm itself, a semiconductor company is likely to pay between $500,000 and $600,000 per set. That price tag rises to around $1m at 90nm, and to $1.5m at 65nm(Figure 2). One recent forecast for […]
Until recently, hierarchical design flows have been favored for the implementation of multi-million gate SOCs. However the rapid increases in design size brought on by nanometer process geometries have seen engineers seek to cope with the inherently block-based nature of such flows by seeking greater concurrency between the block implementation and chip assembly stages in […]
US factory-to-dealer sales of consumer electronics will surpass $155B in 2007, representing 7% growth, according to the most recent forecast from the Consumer Electronics Association. This performance will follow on from an expected $145B market in 2006, a year which surpassed even the most optimistic forecasts by logging growth of 13%. “The industry outlook is […]
There has been a recent trend for tools originally aimed at ASIC designs to be applied to the design of high-volume projects aimed at markets such as consumer electronics. The article argues that there are a number of fundamental flaws in such a strategy. For example, an ASIC tool might be designed for an environment […]
We are now entering the tail end of an era, and many of us do not even know it. For as long as there have been microprocessors, there have been engineers and engineering teams whose job it was to create interconnects. Although this will undoubtedly continue in some companies, the increasing complexity of systems-on-a-chip (SoCs) […]
How do we bridge the gap between the highly abstract view provided by traditional system-level design and the detailed implementation in RTL? The article answers this question by describing the components within an ESL methodology and illustrating its use via customer case studies. The methodology uses the ARM RealView SoC Designer tool and Tenison Design […]
Look at what is supposed to be a stellar-performing market: displays. According to data from the Consumer Electronics Association, large screen plasma and LCDs are flying out of the stores.Yet the major suppliers spent much of Q4 2006 getting seriously beaten up on price. Moreover, the likelihood of a third technology entering that market, SED […]
A major issue faced by SoC design teams adopting 90nm and 65nm process nodes is the increase in yield fall-out. At 90nm it is estimated that 30% of yield fall-out is due to performance and signal integrity issues. As a result, accurate and cost effective at-speed manufacturing test and characterization has become evermore critical to […]
The increasingly onerous nature of physical verification at today’s nanometer process geometries requires the regular benchmarking of appropriate tools, if designs are to be realized in a cost-effective manner. However, the criteria for such benchmarking are all too often limited to relatively simplistic notions of ‘performance’. The article explains that the real cost of physical […]