Start Here

By Chris Edwards |  No Comments  |  Posted: June 1, 2007
Topics/Categories: no topics assigned  |  Tags:

You see, I feel a bit like Columbo. No, my raincoat is not egregiously grubby and I did recently buy a new car, but, well, “Dere’s still one thing dat bothers me.” And it’s this: where is the semiconductor industry going in terms of the placement of risk and capital in the value chain?

Let me give you one example. Configurable processor technology is a very exciting field – it appears to hold quite a few of the answers to today’s ever-shifting dynamics. But then you look at how the configurable guys often get treated in the marketplace.

“Hey, cool stuff,” the client says. “Configurable, you say. Well why don’t you go off and configure it for me, then I’ll buy?” In other words, give me a reference design too.

Rival technologies have little reason to feel smug about this. They are in much the same bind. Many ASIC implementations today are essentially iterations beyond an ASSP, implying a huge absorption of risk beforehand. Or perhaps they are structured from off-the-shelf elements. Meanwhile, the FPGA players are finding it necessary to bundle IP and gates for particular market segments.

Let’s get one thing straight here. I am not questioning the wisdom of these strategies. What the market demands, the market gets, and today the customer really is king. However, it is not clear that silicon has found the right path to full rewards for its contribution.

Methodology is a term we still associate with technical ahead of commercial challenges. The intersection between the design flow and traditional notions of project management (and beyond that, profitability) remains relatively unexplored.

In that context, is there a big opportunity for EDA in all this? After all, its involvement with the industry’s broad client base implies a similarly broad knowledge of design practices and how they feed into the bottom line. That knowledge should certainly hold one part of the answer, if not all of it.

Either way, I would be interested to hear – preferably on a bit more than a post-card – from anyone who is grappling with this topic. Certainly, I can see myself scanning most of DAC’s upcoming management day for some answers as well.

Meanwhile – being an editor rather than an obscenely rich executive who has squared this circle – it is my obligation to round off as ever by thanking this issue’s contributors and you for reading.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors