simulation

February 29, 2016
How to expose X-optimism issues in ASIC and FPGA Design by Lisa Piper

How to expose X-optimism issues in ASIC and FPGA design

Static analysis offers a powerful way of identifying potential X-optimism problems before simulation. The article defines the issue and describes an established solution.
Article  |  Topics: EDA - Verification  |  Tags: , , , , ,   |  Organizations:
December 9, 2015
Emulation IoT Networking Challenges

Emulation overcomes the five main IoT and networking verification challenges

More protocols, multibillion-gate designs, minimized power, burgeoning software and, for networking, hundreds of switch and router ports emphasize the need for scalable, virtualized emulation.
October 28, 2014
Featured image for hybrid testbench article

Harness virtual machines to create an efficient ‘live’ hybrid testbench

This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
July 3, 2014
Pranav Ashar

It’s time to embrace objective-driven verification

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
August 23, 2011

Quantifying returns on litho-friendly design

By the time a serious lithography-related problem is identified at the fab, it is too late in the design process to make simple layout changes. To avoid or reduce design delays, Infineon Technologies uses lithography simulation to detect weak points in a layout and analyze the effect of lithography on the design’s electrical performance. Its [...]
Article  |  Topics: EDA - DFM  |  Tags: , , ,   |  Organizations:

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